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Match Most of Remaining Functions

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This commit is contained in:
PokeCodec
2020-08-14 22:02:49 -04:00
committed by PokeCodec
parent 4ac1b3fec5
commit 26ac9c5faf
14 changed files with 354 additions and 1570 deletions
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asm/crt0.s
+38 -38
View File
@@ -122,10 +122,10 @@ CartIdent:
.align 2, 0
.global start_vector
start_vector:
mov r0, PSR_IRQ_MODE
mov r0, #PSR_IRQ_MODE
msr cpsr_cf, r0
ldr sp, sp_irq
mov r0, PSR_SYS_MODE
mov r0, #PSR_SYS_MODE
msr cpsr_cf, r0
ldr sp, sp_usr
ldr r1, =INTR_VECTOR
@@ -146,76 +146,76 @@ sp_irq: .word IWRAM_END - 0x60
.align 2, 0
.global intr_main
intr_main:
mov r3, REG_BASE
add r3, r3, 0x200
ldr r2, [r3, OFFSET_REG_IE - 0x200]
ldrh r1, [r3, OFFSET_REG_IME - 0x200]
mov r3, #REG_BASE
add r3, r3, #OFFSET_REG_IE
ldr r2, [r3]
ldrh r1, [r3, #REG_IME - REG_IE]
mrs r0, spsr
stmdb sp!, {r0-r3,lr}
mov r0, 0
strh r0, [r3, OFFSET_REG_IME - 0x200]
and r1, r2, r2, lsr 16
mov r12, 0
ands r0, r1, INTR_FLAG_VCOUNT
mov r0, #0
strh r0, [r3, #REG_IME - REG_IE]
and r1, r2, r2, lsr #16
mov r12, #0
ands r0, r1, #INTR_FLAG_VCOUNT
bne jump_intr
add r12, r12, 0x4
mov r0, 0x1
strh r0, [r3, OFFSET_REG_IME - 0x200]
ands r0, r1, INTR_FLAG_SERIAL
strh r0, [r3, #REG_IME - REG_IE]
ands r0, r1, #INTR_FLAG_SERIAL
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_TIMER3
ands r0, r1, #INTR_FLAG_TIMER3
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_HBLANK
ands r0, r1, #INTR_FLAG_HBLANK
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_VBLANK
ands r0, r1, #INTR_FLAG_VBLANK
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_TIMER0
ands r0, r1, #INTR_FLAG_TIMER0
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_TIMER1
ands r0, r1, #INTR_FLAG_TIMER1
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_TIMER2
ands r0, r1, #INTR_FLAG_TIMER2
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_DMA0
ands r0, r1, #INTR_FLAG_DMA0
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_DMA1
ands r0, r1, #INTR_FLAG_DMA1
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_DMA2
ands r0, r1, #INTR_FLAG_DMA2
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_DMA3
ands r0, r1, #INTR_FLAG_DMA3
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_KEYPAD
ands r0, r1, #INTR_FLAG_KEYPAD
bne jump_intr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_GAMEPAK
strbne r0, [r3, OFFSET_REG_SOUNDCNT_X - 0x200]
ands r0, r1, #INTR_FLAG_GAMEPAK
strbne r0, [r3, #REG_SOUNDCNT_X - REG_IE]
loop:
bne loop @ spin
jump_intr:
strh r0, [r3, OFFSET_REG_IF - 0x200]
strh r0, [r3, #REG_IF - REG_IE]
bic r2, r2, r0
ldr r0, =gSTWIStatus
ldr r0, [r0]
ldrb r0, [r0, 0xA]
mov r1, INTR_FLAG_TIMER0
mov r0, r1, lsl r0
orr r0, r0, INTR_FLAG_GAMEPAK
orr r1, r0, INTR_FLAG_SERIAL | INTR_FLAG_TIMER3 | INTR_FLAG_VCOUNT | INTR_FLAG_HBLANK
mov r1, #INTR_FLAG_TIMER0
lsl r0, r1, r0
orr r0, r0, #INTR_FLAG_GAMEPAK
orr r1, r0, #INTR_FLAG_SERIAL | INTR_FLAG_TIMER3 | INTR_FLAG_VCOUNT | INTR_FLAG_HBLANK
and r1, r1, r2
strh r1, [r3, OFFSET_REG_IE - 0x200]
strh r1, [r3, #0]
mrs r3, cpsr
bic r3, r3, PSR_I_BIT | PSR_F_BIT | PSR_MODE_MASK
orr r3, r3, PSR_SYS_MODE
bic r3, r3, #PSR_I_BIT | PSR_F_BIT | PSR_MODE_MASK
orr r3, r3, #PSR_SYS_MODE
msr cpsr_cf, r3
ldr r1, =gIntrTable
add r1, r1, r12
@@ -226,12 +226,12 @@ jump_intr:
intr_return:
ldmia sp!, {lr}
mrs r3, cpsr
bic r3, r3, PSR_I_BIT | PSR_F_BIT | PSR_MODE_MASK
orr r3, r3, PSR_I_BIT | PSR_IRQ_MODE
bic r3, r3, #PSR_I_BIT | PSR_F_BIT | PSR_MODE_MASK
orr r3, r3, #PSR_I_BIT | PSR_IRQ_MODE
msr cpsr_cf, r3
ldmia sp!, {r0-r3,lr}
strh r2, [r3, OFFSET_REG_IE - 0x200]
strh r1, [r3, OFFSET_REG_IME - 0x200]
strh r2, [r3, #0]
strh r1, [r3, #REG_IME - REG_IE]
msr spsr_cf, r0
bx lr
asm/libagbsyscall.s
+14 -14
View File
@@ -7,62 +7,62 @@
thumb_func_start ArcTan2
ArcTan2: @ 81E3B58
swi 0xA
svc 0xA
bx lr
thumb_func_end ArcTan2
thumb_func_start BgAffineSet
BgAffineSet: @ 81E3B5C
swi 0xE
svc 0xE
bx lr
thumb_func_end BgAffineSet
thumb_func_start CpuFastSet
CpuFastSet: @ 81E3B60
swi 0xC
svc 0xC
bx lr
thumb_func_end CpuFastSet
thumb_func_start CpuSet
CpuSet: @ 81E3B64
swi 0xB
svc 0xB
bx lr
thumb_func_end CpuSet
thumb_func_start Div
Div: @ 81E3B68
swi 0x6
svc 0x6
bx lr
thumb_func_end Div
thumb_func_start LZ77UnCompVram
LZ77UnCompVram: @ 81E3B6C
swi 0x12
svc 0x12
bx lr
thumb_func_end LZ77UnCompVram
thumb_func_start LZ77UnCompWram
LZ77UnCompWram: @ 81E3B70
swi 0x11
svc 0x11
bx lr
thumb_func_end LZ77UnCompWram
thumb_func_start MultiBoot
MultiBoot: @ 81E3B74
movs r1, 0x1
swi 0x25
svc 0x25
bx lr
thumb_func_end MultiBoot
thumb_func_start ObjAffineSet
ObjAffineSet: @ 81E3B7C
swi 0xF
svc 0xF
bx lr
thumb_func_end ObjAffineSet
thumb_func_start RegisterRamReset
RegisterRamReset: @ 81E3B80
swi 0x1
svc 0x1
bx lr
thumb_func_end RegisterRamReset
@@ -73,21 +73,21 @@ SoftReset: @ 81E3B84
strb r2, [r3]
ldr r1, =0x03007f00 @ User Stack
mov sp, r1
swi 0x1
swi 0
svc 0x1
svc 0
.pool
thumb_func_end SoftReset
thumb_func_start Sqrt
Sqrt: @ 81E3B9C
swi 0x8
svc 0x8
bx lr
thumb_func_end Sqrt
thumb_func_start VBlankIntrWait
VBlankIntrWait: @ 81E3BA0
movs r2, 0
swi 0x5
svc 0x5
bx lr
thumb_func_end VBlankIntrWait