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through sub_80C4D30

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This commit is contained in:
PikalaxALT
2020-01-07 15:13:48 -05:00
parent 62e29fdc9e
commit b8ec686427
3 changed files with 83 additions and 196 deletions
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asm/region_map.s
-190
View File
@@ -5,196 +5,6 @@
.text .text
thumb_func_start sub_80C4BE4
sub_80C4BE4: @ 80C4BE4
push {lr}
sub sp, 0x8
movs r0, 0
movs r1, 0
str r0, [sp]
str r1, [sp, 0x4]
movs r1, 0
movs r2, 0
bl sub_80C4C2C
movs r0, 0
bl sub_80C4C48
movs r0, 0
mov r1, sp
bl sub_80C4CF0
movs r0, 0x1
mov r1, sp
bl sub_80C4CF0
movs r0, 0
movs r1, 0
bl sub_80C4C74
movs r0, 0
movs r1, 0x1
bl sub_80C4C9C
movs r0, 0x1
movs r1, 0x1
bl sub_80C4C9C
add sp, 0x8
pop {r0}
bx r0
thumb_func_end sub_80C4BE4
thumb_func_start sub_80C4C2C
sub_80C4C2C: @ 80C4C2C
push {lr}
adds r3, r0, 0
lsls r1, 16
lsls r2, 16
lsls r3, 24
orrs r3, r1
orrs r3, r2
lsrs r3, 16
movs r0, 0x50
adds r1, r3, 0
bl SetGpuReg
pop {r0}
bx r0
thumb_func_end sub_80C4C2C
thumb_func_start sub_80C4C48
sub_80C4C48: @ 80C4C48
push {lr}
adds r1, r0, 0
lsls r1, 16
lsrs r1, 16
movs r0, 0x54
bl SetGpuReg
pop {r0}
bx r0
thumb_func_end sub_80C4C48
thumb_func_start sub_80C4C5C
sub_80C4C5C: @ 80C4C5C
push {lr}
adds r2, r0, 0
lsls r1, 16
lsls r2, 24
orrs r2, r1
lsrs r2, 16
movs r0, 0x52
adds r1, r2, 0
bl SetGpuReg
pop {r0}
bx r0
thumb_func_end sub_80C4C5C
thumb_func_start sub_80C4C74
sub_80C4C74: @ 80C4C74
push {lr}
lsls r0, 16
lsls r1, 24
orrs r1, r0
lsrs r1, 16
movs r0, 0x48
bl SetGpuReg
pop {r0}
bx r0
thumb_func_end sub_80C4C74
thumb_func_start sub_80C4C88
sub_80C4C88: @ 80C4C88
push {lr}
adds r1, r0, 0
lsls r1, 16
lsrs r1, 16
movs r0, 0x4A
bl SetGpuReg
pop {r0}
bx r0
thumb_func_end sub_80C4C88
thumb_func_start sub_80C4C9C
sub_80C4C9C: @ 80C4C9C
push {r4,r5,lr}
sub sp, 0x4
lsls r0, 24
lsrs r5, r0, 24
lsls r1, 24
lsrs r4, r1, 24
ldr r1, _080C4CBC @ =gUnknown_83F1CA0
mov r0, sp
movs r2, 0x4
bl memcpy
cmp r4, 0
beq _080C4CC0
cmp r4, 0x1
beq _080C4CDC
b _080C4CE8
.align 2, 0
_080C4CBC: .4byte gUnknown_83F1CA0
_080C4CC0:
movs r0, 0
bl GetGpuReg
adds r1, r0, 0
lsls r0, r5, 1
add r0, sp
ldrh r0, [r0]
orrs r1, r0
lsls r1, 16
lsrs r1, 16
movs r0, 0
bl SetGpuReg
b _080C4CE8
_080C4CDC:
lsls r0, r5, 1
add r0, sp
ldrh r1, [r0]
movs r0, 0
bl ClearGpuRegBits
_080C4CE8:
add sp, 0x4
pop {r4,r5}
pop {r0}
bx r0
thumb_func_end sub_80C4C9C
thumb_func_start sub_80C4CF0
sub_80C4CF0: @ 80C4CF0
push {r4-r6,lr}
adds r4, r0, 0
adds r6, r1, 0
lsls r4, 24
ldr r5, _080C4D2C @ =gUnknown_83F1CA4
lsrs r4, 23
adds r0, r4, r5
ldrb r0, [r0]
ldrh r1, [r6, 0x2]
lsls r1, 8
ldrh r2, [r6, 0x6]
orrs r1, r2
lsls r1, 16
lsrs r1, 16
bl SetGpuReg
adds r5, 0x1
adds r4, r5
ldrb r0, [r4]
ldrh r1, [r6]
lsls r1, 8
ldrh r2, [r6, 0x4]
orrs r1, r2
lsls r1, 16
lsrs r1, 16
bl SetGpuReg
pop {r4-r6}
pop {r0}
bx r0
.align 2, 0
_080C4D2C: .4byte gUnknown_83F1CA4
thumb_func_end sub_80C4CF0
thumb_func_start sub_80C4D30
sub_80C4D30: @ 80C4D30
push {lr}
bl sub_80C4BB8
bl sub_80C4BE4
pop {r0}
bx r0
thumb_func_end sub_80C4D30
thumb_func_start sub_80C4D40 thumb_func_start sub_80C4D40
sub_80C4D40: @ 80C4D40 sub_80C4D40: @ 80C4D40
push {lr} push {lr}
data/region_map.s
+6 -2
View File
@@ -461,10 +461,14 @@ gUnknown_83F1C98:: @ 83F1C98
.4byte gAnimCmd_83F1C8C .4byte gAnimCmd_83F1C8C
gUnknown_83F1CA0:: @ 83F1CA0 gUnknown_83F1CA0:: @ 83F1CA0
.2byte 0x2000, 0x4000 .2byte 0x2000 @ DISPCNT_WIN0_ON
.2byte 0x4000 @ DISPCNT_WIN1_ON
gUnknown_83F1CA4:: @ 83F1CA4 gUnknown_83F1CA4:: @ 83F1CA4
.2byte 0x4044, 0x4246 .byte OFFSET_REG_WIN0V
.byte OFFSET_REG_WIN0H
.byte OFFSET_REG_WIN1V
.byte OFFSET_REG_WIN1H
gUnknown_83F1CA8:: @ 83F1CA8 gUnknown_83F1CA8:: @ 83F1CA8
.byte 15, 1, 2 .byte 15, 1, 2
src/region_map.c
+77 -4
View File
@@ -305,7 +305,7 @@ bool8 sub_80C4B30(u8 a0);
void sub_80C4BE4(void); void sub_80C4BE4(void);
void sub_80C4C2C(u8 a0, u16 a1, u16 a2); void sub_80C4C2C(u8 a0, u16 a1, u16 a2);
void sub_80C4C48(u16 a0); void sub_80C4C48(u16 a0);
void sub_80C4C5C(u16 a0); void sub_80C4C5C(u16 a0, u16 a1);
void sub_80C4C74(u16 a0, u16 a1); void sub_80C4C74(u16 a0, u16 a1);
void sub_80C4C88(u16 a0); void sub_80C4C88(u16 a0);
void sub_80C4C9C(u8 a0, u8 a1); void sub_80C4C9C(u8 a0, u8 a1);
@@ -373,6 +373,8 @@ extern const struct OamData gUnknown_83F1C68;
extern const struct OamData gUnknown_83F1C70; extern const struct OamData gUnknown_83F1C70;
extern const union AnimCmd *const gUnknown_83F1C94[]; extern const union AnimCmd *const gUnknown_83F1C94[];
extern const union AnimCmd *const gUnknown_83F1C98[]; extern const union AnimCmd *const gUnknown_83F1C98[];
extern const u16 gUnknown_83F1CA0[];
extern const u8 gUnknown_83F1CA4[][2];
extern const u8 *const gUnknown_83F1CAC[]; extern const u8 *const gUnknown_83F1CAC[];
extern const u16 gUnknown_83F1E60[][2]; extern const u16 gUnknown_83F1E60[][2];
extern const u16 gUnknown_83F2178[][2]; extern const u16 gUnknown_83F2178[][2];
@@ -1034,14 +1036,14 @@ void sub_80C0FE0(void)
{ {
sub_80C4BE4(); sub_80C4BE4();
sub_80C4C2C(27, 4, 64); sub_80C4C2C(27, 4, 64);
sub_80C4C5C(16 - gUnknown_20399D8->field_1CCD); sub_80C4C5C(16 - gUnknown_20399D8->field_1CCD, gUnknown_20399D8->field_1CCD);
} }
bool8 sub_80C1014(void) bool8 sub_80C1014(void)
{ {
if (gUnknown_20399D8->field_1CCD < 16) if (gUnknown_20399D8->field_1CCD < 16)
{ {
sub_80C4C5C(16 - gUnknown_20399D8->field_1CCD); sub_80C4C5C(16 - gUnknown_20399D8->field_1CCD, gUnknown_20399D8->field_1CCD);
gUnknown_20399D8->field_1CCD += 2; gUnknown_20399D8->field_1CCD += 2;
return FALSE; return FALSE;
} }
@@ -1056,7 +1058,7 @@ bool8 sub_80C1058(void)
if (gUnknown_20399D8->field_1CCD >= 2) if (gUnknown_20399D8->field_1CCD >= 2)
{ {
gUnknown_20399D8->field_1CCD -= 2; gUnknown_20399D8->field_1CCD -= 2;
sub_80C4C5C(16 - gUnknown_20399D8->field_1CCD); sub_80C4C5C(16 - gUnknown_20399D8->field_1CCD, gUnknown_20399D8->field_1CCD);
return FALSE; return FALSE;
} }
else else
@@ -3140,3 +3142,74 @@ void sub_80C4BB8(void)
FREE_IF_NOT_NULL(gUnknown_20399F0[i]); FREE_IF_NOT_NULL(gUnknown_20399F0[i]);
} }
} }
void sub_80C4BE4(void)
{
struct UnkStruct_80C4CF0 data = {};
sub_80C4C2C(0, 0, 0);
sub_80C4C48(0);
sub_80C4CF0(0, &data);
sub_80C4CF0(1, &data);
sub_80C4C74(0, 0);
sub_80C4C9C(0, 1);
sub_80C4C9C(1, 1);
}
void sub_80C4C2C(u8 a0, u16 a1, u16 a2)
{
u16 regval = a0 << 8;
regval |= a1;
regval |= a2;
SetGpuReg(REG_OFFSET_BLDCNT, regval);
}
void sub_80C4C48(u16 a0)
{
SetGpuReg(REG_OFFSET_BLDY, a0);
}
void sub_80C4C5C(u16 a0, u16 a1)
{
u16 regval = a0 << 8;
regval |= a1;
SetGpuReg(REG_OFFSET_BLDALPHA, regval);
}
void sub_80C4C74(u16 a0, u16 a1)
{
u16 regval = a1 << 8;
regval |= a0;
SetGpuReg(REG_OFFSET_WININ, regval);
}
void sub_80C4C88(u16 a0)
{
SetGpuReg(REG_OFFSET_WINOUT, a0);
}
void sub_80C4C9C(u8 a0, u8 a1)
{
u16 data[2];
memcpy(data, gUnknown_83F1CA0, 4);
switch (a1)
{
case 0:
SetGpuReg(REG_OFFSET_DISPCNT, GetGpuReg(REG_OFFSET_DISPCNT) | data[a0]);
break;
case 1:
ClearGpuRegBits(REG_OFFSET_DISPCNT, data[a0]);
break;
}
}
void sub_80C4CF0(u8 a0, const struct UnkStruct_80C4CF0 *a1)
{
SetGpuReg(gUnknown_83F1CA4[a0][0], (a1->v2 << 8) | a1->v6);
SetGpuReg(gUnknown_83F1CA4[a0][1], (a1->v0 << 8) | a1->v4);
}
void sub_80C4D30(void)
{
sub_80C4BB8();
sub_80C4BE4();
}