nonmatching sub_800FD14
This commit is contained in:
PikalaxALT
201
src/link_rfu.c
201
src/link_rfu.c
@@ -3548,3 +3548,204 @@ u8 sub_800FCD8(void)
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}
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return flags;
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}
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#ifdef NONMATCHING
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// The switch tree is incorrect
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void sub_800FD14(u16 command)
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{
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u8 i;
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u8 *buff;
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u8 tmp;
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gSendCmd[0] = command;
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switch (command)
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{
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case 0x8800:
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gSendCmd[1] = gUnknown_03005000.unk_6c.unk_02;
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gSendCmd[2] = gUnknown_03005000.unk_6c.unk_11 + 0x80;
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break;
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case 0xa100:
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if (sub_800FC60())
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gSendCmd[1] = gUnknown_03005000.unk_5a;
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break;
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case 0x7800:
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case 0x7700:
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tmp = gUnknown_03005000.unk_ce2 ^ gUnknown_03005000.unk_ce3;
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gUnknown_03005000.playerCount = gUnknown_082ED695[tmp] + 1;
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gSendCmd[1] = gUnknown_03005000.playerCount;
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buff = (u8 *)(gSendCmd + 2);
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for (i = 0; i < 4; i++)
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buff[i] = gUnknown_03005000.unk_cde[i];
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break;
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case 0x6600:
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case 0x5f00:
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gSendCmd[1] = gUnknown_03005000.unk_100;
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break;
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case 0x4400:
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gSendCmd[0] = 0x4400;
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gSendCmd[1] = gMain.heldKeys;
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break;
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case 0x2f00:
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for (i = 0; i < 6; i++)
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gSendCmd[1 + i] = gUnknown_03005000.unk_f2[i];
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break;
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case 0xbe00:
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gSendCmd[1] = gUnknown_03005DA8;
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break;
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}
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}
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#else
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__attribute__((naked)) void sub_800FD14(u16 command)
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{
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asm_unified("\tpush {r4,r5,lr}\n"
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"\tlsls r0, 16\n"
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"\tlsrs r1, r0, 16\n"
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"\tldr r5, =gSendCmd\n"
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"\tstrh r1, [r5]\n"
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"\tmovs r0, 0xF0\n"
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"\tlsls r0, 7\n"
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"\tadds r4, r5, 0\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FDB0_case_7700_case_7800\n"
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"\tcmp r1, r0\n"
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"\tbgt _0800FD62\n"
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"\tmovs r0, 0xBE\n"
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"\tlsls r0, 7\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FE00_case_5f00_case_6600\n"
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"\tcmp r1, r0\n"
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"\tbgt _0800FD50\n"
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"\tmovs r0, 0xBC\n"
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"\tlsls r0, 6\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FE20_case_2f00\n"
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"\tmovs r0, 0x88\n"
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"\tlsls r0, 7\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FE14_case_4400\n"
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"\tb _0800FE46_break\n"
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"\t.pool\n"
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"_0800FD50:\n"
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"\tmovs r0, 0xCC\n"
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"\tlsls r0, 7\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FE00_case_5f00_case_6600\n"
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"\tmovs r0, 0xEE\n"
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"\tlsls r0, 7\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FDB0_case_7700_case_7800\n"
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"\tb _0800FE46_break\n"
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"_0800FD62:\n"
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"\tmovs r0, 0xBE\n"
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"\tlsls r0, 8\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FE40_case_be00\n"
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"\tcmp r1, r0\n"
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"\tbgt _0800FE46_break\n"
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"\tmovs r0, 0x88\n"
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"\tlsls r0, 8\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FD80_case_8800\n"
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"\tmovs r0, 0xA1\n"
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"\tlsls r0, 8\n"
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"\tcmp r1, r0\n"
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"\tbeq _0800FD98_case_a100\n"
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"\tb _0800FE46_break\n"
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"_0800FD80_case_8800:\n"
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"\tldr r0, =gUnknown_03005000\n"
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"\tadds r1, r0, 0\n"
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"\tadds r1, 0x6E\n"
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"\tldrh r1, [r1]\n"
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"\tstrh r1, [r5, 0x2]\n"
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"\tadds r0, 0x7D\n"
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"\tldrb r0, [r0]\n"
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"\tadds r0, 0x80\n"
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"\tstrh r0, [r5, 0x4]\n"
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"\tb _0800FE46_break\n"
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"\t.pool\n"
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"_0800FD98_case_a100:\n"
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"\tbl sub_800FC60\n"
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"\tlsls r0, 24\n"
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"\tcmp r0, 0\n"
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"\tbeq _0800FE46_break\n"
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"\tldr r0, =gUnknown_03005000\n"
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"\tadds r0, 0x5A\n"
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"\tldrb r0, [r0]\n"
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"\tb _0800FE44_str_break\n"
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"\t.pool\n"
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"_0800FDB0_case_7700_case_7800:\n"
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"\tldr r3, =gUnknown_03005000\n"
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"\tldr r1, =0x00000ce2\n"
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"\tadds r0, r3, r1\n"
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"\tldr r2, =0x00000ce3\n"
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"\tadds r1, r3, r2\n"
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"\tldrb r2, [r0]\n"
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"\tldrb r0, [r1]\n"
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"\teors r0, r2\n"
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"\tldr r1, =gUnknown_082ED695\n"
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"\tadds r0, r1\n"
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"\tldrb r0, [r0]\n"
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"\tadds r0, 0x1\n"
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"\tstrb r0, [r3, 0xD]\n"
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"\tldrb r0, [r3, 0xD]\n"
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"\tstrh r0, [r4, 0x2]\n"
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"\tadds r2, r4, 0x4\n"
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"\tmovs r4, 0\n"
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"\tldr r0, =0x00000cde\n"
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"\tadds r3, r0\n"
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"_0800FDD6:\n"
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"\tadds r1, r2, r4\n"
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"\tadds r0, r4, r3\n"
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"\tldrb r0, [r0]\n"
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"\tstrb r0, [r1]\n"
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"\tadds r0, r4, 0x1\n"
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"\tlsls r0, 24\n"
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"\tlsrs r4, r0, 24\n"
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"\tcmp r4, 0x3\n"
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"\tbls _0800FDD6\n"
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"\tb _0800FE46_break\n"
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"\t.pool\n"
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"_0800FE00_case_5f00_case_6600:\n"
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"\tldr r0, =gUnknown_03005000\n"
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"\tmovs r1, 0x80\n"
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"\tlsls r1, 1\n"
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"\tadds r0, r1\n"
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"\tldrh r0, [r0]\n"
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"\tstrh r0, [r4, 0x2]\n"
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"\tb _0800FE46_break\n"
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"\t.pool\n"
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"_0800FE14_case_4400:\n"
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"\tstrh r1, [r5]\n"
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"\tldr r0, =gMain\n"
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"\tldrh r0, [r0, 0x2C]\n"
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"\tb _0800FE44_str_break\n"
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"\t.pool\n"
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"_0800FE20_case_2f00:\n"
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"\tmovs r4, 0\n"
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"\tldr r3, =gUnknown_03005000+0xF2\n"
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"_0800FE24:\n"
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"\tadds r2, r4, 0x1\n"
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"\tlsls r1, r2, 1\n"
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"\tadds r1, r5\n"
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"\tlsls r0, r4, 1\n"
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"\tadds r0, r3\n"
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"\tldrh r0, [r0]\n"
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"\tstrh r0, [r1]\n"
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"\tlsls r2, 24\n"
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"\tlsrs r4, r2, 24\n"
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"\tcmp r4, 0x5\n"
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"\tbls _0800FE24\n"
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"\tb _0800FE46_break\n"
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"\t.pool\n"
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"_0800FE40_case_be00:\n"
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"\tldr r0, =gUnknown_03005DA8\n"
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"\tldrh r0, [r0]\n"
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"_0800FE44_str_break:\n"
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"\tstrh r0, [r5, 0x2]\n"
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"_0800FE46_break:\n"
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"\tpop {r4,r5}\n"
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"\tpop {r0}\n"
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"\tbx r0\n"
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"\t.pool");
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}
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#endif
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