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Remove uses of INVALID_ defines, clean up some arrays with constants, and spaces -> tabs

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nullableVoidPtr
2018-12-05 22:31:01 +08:00
parent 405f1bb529
commit f9ff7316d5
140 changed files with 27697 additions and 23904 deletions
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192
src/gpu_regs.c
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@@ -20,166 +20,166 @@ static void UpdateRegDispstatIntrBits(u16 regIE);
void InitGpuRegManager(void)
{
s32 i;
s32 i;
for (i = 0; i < GPU_REG_BUF_SIZE; i++)
for (i = 0; i < GPU_REG_BUF_SIZE; i++)
{
sGpuRegBuffer[i] = 0;
sGpuRegWaitingList[i] = EMPTY_SLOT;
}
sGpuRegBuffer[i] = 0;
sGpuRegWaitingList[i] = EMPTY_SLOT;
}
sGpuRegBufferLocked = FALSE;
sShouldSyncRegIE = FALSE;
sRegIE = 0;
sGpuRegBufferLocked = FALSE;
sShouldSyncRegIE = FALSE;
sRegIE = 0;
}
static void CopyBufferedValueToGpuReg(u8 regOffset)
{
if (regOffset == REG_OFFSET_DISPSTAT)
if (regOffset == REG_OFFSET_DISPSTAT)
{
REG_DISPSTAT &= ~(DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
REG_DISPSTAT |= GPU_REG_BUF(REG_OFFSET_DISPSTAT);
}
else
REG_DISPSTAT &= ~(DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
REG_DISPSTAT |= GPU_REG_BUF(REG_OFFSET_DISPSTAT);
}
else
{
GPU_REG(regOffset) = GPU_REG_BUF(regOffset);
}
GPU_REG(regOffset) = GPU_REG_BUF(regOffset);
}
}
void CopyBufferedValuesToGpuRegs(void)
{
if (!sGpuRegBufferLocked)
if (!sGpuRegBufferLocked)
{
s32 i;
s32 i;
for (i = 0; i < GPU_REG_BUF_SIZE; i++)
for (i = 0; i < GPU_REG_BUF_SIZE; i++)
{
u8 regOffset = sGpuRegWaitingList[i];
if (regOffset == EMPTY_SLOT)
return;
CopyBufferedValueToGpuReg(regOffset);
sGpuRegWaitingList[i] = EMPTY_SLOT;
}
}
u8 regOffset = sGpuRegWaitingList[i];
if (regOffset == EMPTY_SLOT)
return;
CopyBufferedValueToGpuReg(regOffset);
sGpuRegWaitingList[i] = EMPTY_SLOT;
}
}
}
void SetGpuReg(u8 regOffset, u16 value)
{
if (regOffset < GPU_REG_BUF_SIZE)
{
u16 vcount;
if (regOffset < GPU_REG_BUF_SIZE)
{
u16 vcount;
GPU_REG_BUF(regOffset) = value;
vcount = REG_VCOUNT & 0xFF;
GPU_REG_BUF(regOffset) = value;
vcount = REG_VCOUNT & 0xFF;
if ((vcount >= 161 && vcount <= 225)
|| (REG_DISPCNT & DISPCNT_FORCED_BLANK)) {
CopyBufferedValueToGpuReg(regOffset);
} else {
s32 i;
if ((vcount >= 161 && vcount <= 225)
|| (REG_DISPCNT & DISPCNT_FORCED_BLANK)) {
CopyBufferedValueToGpuReg(regOffset);
} else {
s32 i;
sGpuRegBufferLocked = TRUE;
sGpuRegBufferLocked = TRUE;
for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++) {
if (sGpuRegWaitingList[i] == regOffset) {
sGpuRegBufferLocked = FALSE;
return;
}
}
for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++) {
if (sGpuRegWaitingList[i] == regOffset) {
sGpuRegBufferLocked = FALSE;
return;
}
}
sGpuRegWaitingList[i] = regOffset;
sGpuRegBufferLocked = FALSE;
}
}
sGpuRegWaitingList[i] = regOffset;
sGpuRegBufferLocked = FALSE;
}
}
}
void SetGpuReg_ForcedBlank(u8 regOffset, u16 value)
{
if (regOffset < GPU_REG_BUF_SIZE)
{
GPU_REG_BUF(regOffset) = value;
if (regOffset < GPU_REG_BUF_SIZE)
{
GPU_REG_BUF(regOffset) = value;
if (REG_DISPCNT & DISPCNT_FORCED_BLANK) {
CopyBufferedValueToGpuReg(regOffset);
} else {
s32 i;
if (REG_DISPCNT & DISPCNT_FORCED_BLANK) {
CopyBufferedValueToGpuReg(regOffset);
} else {
s32 i;
sGpuRegBufferLocked = TRUE;
sGpuRegBufferLocked = TRUE;
for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++) {
if (sGpuRegWaitingList[i] == regOffset) {
sGpuRegBufferLocked = FALSE;
return;
}
}
for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++) {
if (sGpuRegWaitingList[i] == regOffset) {
sGpuRegBufferLocked = FALSE;
return;
}
}
sGpuRegWaitingList[i] = regOffset;
sGpuRegBufferLocked = FALSE;
}
}
sGpuRegWaitingList[i] = regOffset;
sGpuRegBufferLocked = FALSE;
}
}
}
u16 GetGpuReg(u8 regOffset)
{
if (regOffset == REG_OFFSET_DISPSTAT)
return REG_DISPSTAT;
if (regOffset == REG_OFFSET_DISPSTAT)
return REG_DISPSTAT;
if (regOffset == REG_OFFSET_VCOUNT)
return REG_VCOUNT;
if (regOffset == REG_OFFSET_VCOUNT)
return REG_VCOUNT;
return GPU_REG_BUF(regOffset);
return GPU_REG_BUF(regOffset);
}
void SetGpuRegBits(u8 regOffset, u16 mask)
{
u16 regValue = GPU_REG_BUF(regOffset);
SetGpuReg(regOffset, regValue | mask);
u16 regValue = GPU_REG_BUF(regOffset);
SetGpuReg(regOffset, regValue | mask);
}
void ClearGpuRegBits(u8 regOffset, u16 mask)
{
u16 regValue = GPU_REG_BUF(regOffset);
SetGpuReg(regOffset, regValue & ~mask);
u16 regValue = GPU_REG_BUF(regOffset);
SetGpuReg(regOffset, regValue & ~mask);
}
static void SyncRegIE(void)
{
if (sShouldSyncRegIE) {
u16 temp = REG_IME;
REG_IME = 0;
REG_IE = sRegIE;
REG_IME = temp;
sShouldSyncRegIE = FALSE;
}
if (sShouldSyncRegIE) {
u16 temp = REG_IME;
REG_IME = 0;
REG_IE = sRegIE;
REG_IME = temp;
sShouldSyncRegIE = FALSE;
}
}
void EnableInterrupts(u16 mask)
{
sRegIE |= mask;
sShouldSyncRegIE = TRUE;
SyncRegIE();
UpdateRegDispstatIntrBits(sRegIE);
sRegIE |= mask;
sShouldSyncRegIE = TRUE;
SyncRegIE();
UpdateRegDispstatIntrBits(sRegIE);
}
void DisableInterrupts(u16 mask)
{
sRegIE &= ~mask;
sShouldSyncRegIE = TRUE;
SyncRegIE();
UpdateRegDispstatIntrBits(sRegIE);
sRegIE &= ~mask;
sShouldSyncRegIE = TRUE;
SyncRegIE();
UpdateRegDispstatIntrBits(sRegIE);
}
static void UpdateRegDispstatIntrBits(u16 regIE)
{
u16 oldValue = GetGpuReg(REG_OFFSET_DISPSTAT) & (DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
u16 newValue = 0;
u16 oldValue = GetGpuReg(REG_OFFSET_DISPSTAT) & (DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
u16 newValue = 0;
if (regIE & INTR_FLAG_VBLANK)
newValue |= DISPSTAT_VBLANK_INTR;
if (regIE & INTR_FLAG_VBLANK)
newValue |= DISPSTAT_VBLANK_INTR;
if (regIE & INTR_FLAG_HBLANK)
newValue |= DISPSTAT_HBLANK_INTR;
if (regIE & INTR_FLAG_HBLANK)
newValue |= DISPSTAT_HBLANK_INTR;
if (oldValue != newValue)
SetGpuReg(REG_OFFSET_DISPSTAT, newValue);
if (oldValue != newValue)
SetGpuReg(REG_OFFSET_DISPSTAT, newValue);
}