Payload is now independent of agbsdk
Are you happy now @luckytyphlosion? Kappa
This commit is contained in:
PikalaxALT
@@ -16,7 +16,7 @@ CPPFLAGS := -I ../../tools/agbcc/include -I ../../tools/agbcc -iquote include -n
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ROM := payload.gba
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OBJ_DIR := build
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CC1 := ../../tools/agbcc/bin/agbcc$(EXE)
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override CFLAGS += -mthumb-interwork -Wimplicit -Wparentheses -Werror -O2 -fhex-asm
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override CC1FLAGS += -mthumb-interwork -Wimplicit -Wparentheses -Werror -O2 -fhex-asm
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ELF = $(ROM:.gba=.elf)
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@@ -34,7 +34,7 @@ ASFLAGS := -mcpu=arm7tdmi
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LDFLAGS = -Map ../$(MAP)
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LIB := -L ../../../tools/agbcc/lib -lagb_flash -lsiirtc -lagbsyscall -lgcc
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LIB := -L ../../../tools/agbcc/lib -lgcc
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SHA1 := $(shell { command -v sha1sum || command -v shasum; } 2>/dev/null) -c
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GFX := ../../tools/gbagfx/gbagfx$(EXE)
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@@ -79,6 +79,12 @@ SUBDIRS := $(sort $(dir $(OBJS)))
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$(shell mkdir -p $(SUBDIRS))
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$(C_BUILDDIR)/siirtc.o: CC1FLAGS := -mthumb-interwork
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$(C_BUILDDIR)/agb_flash.o: CC1FLAGS := -O1 -mthumb-interwork
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$(C_BUILDDIR)/agb_flash_1m.o: CC1FLAGS := -O1 -mthumb-interwork
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$(C_BUILDDIR)/agb_flash_mx.o: CC1FLAGS := -O1 -mthumb-interwork
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$(C_BUILDDIR)/agb_flash_le.o: CC1FLAGS := -O1 -mthumb-interwork
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rom: $(ROM)
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# For contributors to make sure a change didn't affect the contents of the ROM.
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@@ -116,7 +122,7 @@ endif
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$(C_BUILDDIR)/%.o : $(C_SUBDIR)/%.c $$(c_dep)
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@$(CPP) $(CPPFLAGS) $< -o $(C_BUILDDIR)/$*.i
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@$(PREPROC) $(C_BUILDDIR)/$*.i charmap.txt | $(CC1) $(CFLAGS) -o $(C_BUILDDIR)/$*.s
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@$(PREPROC) $(C_BUILDDIR)/$*.i charmap.txt | $(CC1) $(CC1FLAGS) -o $(C_BUILDDIR)/$*.s
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$(AS) $(ASFLAGS) -o $@ $(C_BUILDDIR)/$*.s
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ifeq ($(NODEP),1)
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@@ -0,0 +1,46 @@
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.include "constants/gba_constants.inc"
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.include "asm/macros.inc"
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.syntax unified
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.text
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thumb_func_start CpuSet
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CpuSet: @ 81E3B64
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swi 0xB
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bx lr
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thumb_func_end CpuSet
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thumb_func_start Div
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Div: @ 81E3B68
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swi 0x6
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bx lr
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thumb_func_end Div
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thumb_func_start Mod
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Mod:
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swi 0x6
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adds r0, r1, 0
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bx lr
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thumb_func_end Mod
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thumb_func_start LZ77UnCompVram
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LZ77UnCompVram: @ 81E3B6C
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swi 0x12
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bx lr
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thumb_func_end LZ77UnCompVram
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thumb_func_start RegisterRamReset
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RegisterRamReset: @ 81E3B80
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swi 0x1
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bx lr
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thumb_func_end RegisterRamReset
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thumb_func_start VBlankIntrWait
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VBlankIntrWait: @ 81E3BA0
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movs r2, 0
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swi 0x5
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bx lr
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thumb_func_end VBlankIntrWait
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.align 2, 0 @ Don't pad with nop.
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@@ -0,0 +1,155 @@
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.include "asm/macros/asm.inc"
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.include "asm/macros/function.inc"
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.include "asm/macros/movement.inc"
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.include "asm/macros/pokemon_data.inc"
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.include "asm/macros/ec.inc"
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.include "asm/macros/map.inc"
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.include "asm/macros/m4a.inc"
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.macro region_map_location x, y, width, height, name
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.byte \x
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.byte \y
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.byte \width
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.byte \height
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.4byte gMapName_\name
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.endm
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.macro obj_tiles address, uncompressed_size, tag
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.4byte \address
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.2byte \uncompressed_size
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.2byte \tag
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.endm
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.macro null_obj_tiles
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obj_tiles 0, 0, 0
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.endm
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.macro obj_pal address, tag
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.4byte \address
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.2byte \tag
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.2byte 0 @ padding
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.endm
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.macro null_obj_pal
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obj_pal 0, 0
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.endm
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.macro paired_pals tag, address
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.2byte \tag
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.2byte 0 @ padding
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.4byte \address
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.endm
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@ For object animation frames.
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.macro obj_frame_tiles address, uncompressed_size
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.4byte \address
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.2byte \uncompressed_size
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.2byte 0 @ padding
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.endm
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.macro spr_template tile_tag, pal_tag, oam, anims, images, affine_anims, callback
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.2byte \tile_tag
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.2byte \pal_tag
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.4byte \oam
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.4byte \anims
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.4byte \images
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.4byte \affine_anims
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.4byte \callback
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.endm
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@ Berry trees have a table defining the palette slot used for each of their 5
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@ stages. However, the first 2 stages always use the same slots regardless of
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@ the type of tree and the slots of the last 3 stages always equal each other.
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.macro berry_tree_palette_slot_table slot
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.byte 3, 4, \slot, \slot, \slot
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.endm
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.macro subsprite x, y, priority, tile_num_offset, size
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.2byte \x
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.2byte \y
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.2byte ((\priority) << 14) | ((\tile_num_offset) << 4) | SPRITE_SIZE_\size
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.2byte 0 @ padding
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.endm
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.macro obj_image_anim_frame pic_id, duration, flags = 0
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.2byte \pic_id
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.byte (\flags) | (\duration)
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.byte 0 @ padding
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.endm
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.macro obj_image_anim_loop count
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.2byte 0xfffd
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.byte \count
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.byte 0 @ padding
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.endm
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.macro obj_image_anim_jump target_index
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.2byte 0xfffe
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.byte \target_index
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.byte 0 @ padding
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.endm
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.macro obj_image_anim_end
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.2byte 0xffff
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.2byte 0 @ padding
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.endm
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.macro obj_rot_scal_anim_frame delta_x_scale, delta_y_scale, delta_angle, duration
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.2byte \delta_x_scale
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.2byte \delta_y_scale
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.byte \delta_angle
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.byte \duration
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.2byte 0 @ padding
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.endm
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.macro obj_rot_scal_anim_loop count
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.2byte 0x7ffd
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.2byte \count
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.4byte 0 @ padding
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.endm
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.macro obj_rot_scal_anim_jump target_index
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.2byte 0x7ffe
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.2byte \target_index
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.4byte 0 @ padding
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.endm
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.macro obj_rot_scal_anim_end unknown=0
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.2byte 0x7fff
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.2byte \unknown
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.fill 4 @ padding
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.endm
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.macro credits_entry number, text
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.4byte \number
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.4byte \text
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.endm
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.macro door_anim_frame unknown, offset
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.byte \unknown
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.byte 0 @ padding
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.2byte \offset
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.endm
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.macro door_anim_gfx metatile_num, unknown, tile_addr, palette_addr
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.2byte \metatile_num
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.2byte \unknown
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.4byte \tile_addr
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.4byte \palette_addr
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.endm
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.macro trainer_eye_trainer opp_1, opp_2, opp_3, opp_4, opp_5, map_name
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.2byte OPPONENT_\opp_1
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.2byte OPPONENT_\opp_2
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.2byte OPPONENT_\opp_3
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.2byte OPPONENT_\opp_4
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.2byte OPPONENT_\opp_5
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.2byte GROUP_\map_name
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.2byte MAP_\map_name
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.space 2
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.endm
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.macro window_template bg, top, left, height, width, palno, baseBlock
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.byte \bg, \top, \left, \height, \width, \palno
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.2byte \baseBlock
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.endm
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@@ -0,0 +1,17 @@
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.ifndef GUARD_ASM_MACROS_ASM_INC
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.set GUARD_ASM_MACROS_ASM_INC, 1
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.macro inc x
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.set \x, \x + 1
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.endm
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.macro enum_start x=0
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.set __enum__, \x
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.endm
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.macro enum constant
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.equiv \constant, __enum__
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inc __enum__
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.endm
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.endif @ GUARD_ASM_MACROS_ASM_INC
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@@ -0,0 +1,554 @@
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.macro if_random_less_than percent, address
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.byte 0x00
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.byte \percent
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.4byte \address
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.endm
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@ unused
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.macro if_random_greater_than percent, address
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.byte 0x01
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.byte \percent
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.4byte \address
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.endm
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@ unused
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.macro if_random_equal address
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.byte 0x02
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.4byte \address
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.endm
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@ unused
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.macro if_random_not_equal address
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.byte 0x03
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.4byte \address
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.endm
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.macro score score
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.byte 0x04
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.byte \score
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.endm
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.macro if_hp_less_than target, percent, address
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.byte 0x05
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.byte \target
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.byte \percent
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.4byte \address
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.endm
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.macro if_hp_more_than target, percent, address
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.byte 0x06
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.byte \target
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.byte \percent
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.4byte \address
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.endm
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.macro if_hp_equal target, percent, address
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.byte 0x07
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.byte \target
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.byte \percent
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.4byte \address
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.endm
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.macro if_hp_not_equal target, percent, address
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.byte 0x08
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.byte \target
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.byte \percent
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.4byte \address
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.endm
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.macro if_status target, status, address
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.byte 0x09
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.byte \target
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.4byte \status
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.4byte \address
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.endm
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.macro if_not_status target, status, address
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.byte 0x0a
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.byte \target
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.4byte \status
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.4byte \address
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.endm
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.macro if_status2 target, status, address
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.byte 0x0b
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.byte \target
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.4byte \status
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.4byte \address
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.endm
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.macro if_not_status2 target, status, address
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.byte 0x0c
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.byte \target
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.4byte \status
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.4byte \address
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.endm
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.macro if_status3 target, status, address
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.byte 0x0d
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.byte \target
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.4byte \status
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.4byte \address
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.endm
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.macro if_not_status3 target, status, address
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.byte 0x0e
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.byte \target
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.4byte \status
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.4byte \address
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.endm
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.macro if_status4 target, status, address
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.byte 0x0f
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.byte \target
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.4byte \status
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.4byte \address
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.endm
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.macro if_not_status4 target, status, address
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.byte 0x10
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.byte \target
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.4byte \status
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.4byte \address
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.endm
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.macro if_less_than value, address
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.byte 0x11
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.byte \value
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.4byte \address
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.endm
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.macro if_more_than value, address
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.byte 0x12
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.byte \value
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.4byte \address
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.endm
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.macro if_equal value, address
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.byte 0x13
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||||
.byte \value
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.4byte \address
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||||
.endm
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||||
|
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.macro if_not_equal value, address
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.byte 0x14
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||||
.byte \value
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||||
.4byte \address
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||||
.endm
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||||
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.macro if_less_than_32 value, address
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||||
.byte 0x15
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||||
.4byte \value
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||||
.4byte \address
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||||
.endm
|
||||
|
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.macro if_more_than_32 value, address
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.byte 0x16
|
||||
.4byte \value
|
||||
.4byte \address
|
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.endm
|
||||
|
||||
.macro if_equal_32 value, address
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||||
.byte 0x17
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||||
.4byte \value
|
||||
.4byte \address
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.endm
|
||||
|
||||
.macro if_not_equal_32 value, address
|
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.byte 0x18
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.4byte \value
|
||||
.4byte \address
|
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.endm
|
||||
|
||||
.macro if_move move, address
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.byte 0x19
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||||
.2byte \move
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||||
.4byte \address
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||||
.endm
|
||||
|
||||
.macro if_not_move move, address
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||||
.byte 0x1a
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||||
.2byte \move
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||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_in_bytes list, address
|
||||
.byte 0x1b
|
||||
.4byte \list
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_not_in_bytes list, address
|
||||
.byte 0x1c
|
||||
.4byte \list
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_in_words list, address
|
||||
.byte 0x1d
|
||||
.4byte \list
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_not_in_words list, address
|
||||
.byte 0x1e
|
||||
.4byte \list
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_user_can_damage address
|
||||
.byte 0x1f
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_user_cant_damage address
|
||||
.byte 0x20
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro get_turn_count
|
||||
.byte 0x21
|
||||
.endm
|
||||
|
||||
.macro get_type byte
|
||||
.byte 0x22
|
||||
.byte \byte
|
||||
.endm
|
||||
|
||||
@ unused
|
||||
.macro get_move_power
|
||||
.byte 0x23
|
||||
.endm
|
||||
|
||||
.macro is_most_powerful_move
|
||||
.byte 0x24
|
||||
.endm
|
||||
|
||||
.macro get_move target
|
||||
.byte 0x25
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
.macro if_arg_equal type, address
|
||||
.byte 0x26
|
||||
.byte \type
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
@ unused
|
||||
.macro if_arg_not_equal type, address
|
||||
.byte 0x27
|
||||
.byte \type
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_would_go_first target, address
|
||||
.byte 0x28
|
||||
.byte \target
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_would_not_go_first target, address
|
||||
.byte 0x29
|
||||
.byte \target
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_2a
|
||||
.byte 0x2a
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_2b
|
||||
.byte 0x2b
|
||||
.endm
|
||||
|
||||
.macro count_alive_pokemon target
|
||||
.byte 0x2c
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
@ unused
|
||||
.macro get_considered_move
|
||||
.byte 0x2d
|
||||
.endm
|
||||
|
||||
.macro get_effect
|
||||
.byte 0x2e
|
||||
.endm
|
||||
|
||||
.macro get_ability target
|
||||
.byte 0x2f
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
@ unused
|
||||
.macro get_highest_possible_damage
|
||||
.byte 0x30
|
||||
.endm
|
||||
|
||||
.macro if_damage_bonus value, address
|
||||
.byte 0x31
|
||||
.byte \value
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_32
|
||||
.byte 0x32
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_33
|
||||
.byte 0x33
|
||||
.endm
|
||||
|
||||
.macro if_status_in_party target, status, address
|
||||
.byte 0x34
|
||||
.byte \target
|
||||
.4byte \status
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
@ bugged
|
||||
.macro if_status_not_in_party target, status, address
|
||||
.byte 0x35
|
||||
.byte \target
|
||||
.4byte \status
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro get_weather
|
||||
.byte 0x36
|
||||
.endm
|
||||
|
||||
.macro if_effect byte, address
|
||||
.byte 0x37
|
||||
.byte \byte
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_not_effect byte, address
|
||||
.byte 0x38
|
||||
.byte \byte
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_stat_level_less_than target, stat, level, address
|
||||
.byte 0x39
|
||||
.byte \target
|
||||
.byte \stat
|
||||
.byte \level
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_stat_level_more_than target, stat, level, address
|
||||
.byte 0x3a
|
||||
.byte \target
|
||||
.byte \stat
|
||||
.byte \level
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_stat_level_equal target, stat, level, address
|
||||
.byte 0x3b
|
||||
.byte \target
|
||||
.byte \stat
|
||||
.byte \level
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_stat_level_not_equal target, stat, level, address
|
||||
.byte 0x3c
|
||||
.byte \target
|
||||
.byte \stat
|
||||
.byte \level
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_can_faint address
|
||||
.byte 0x3d
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_cant_faint address
|
||||
.byte 0x3e
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
@ unused
|
||||
.macro if_has_move, target, move, address
|
||||
.byte 0x3f
|
||||
.byte \target
|
||||
.2byte \move
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
@ unused
|
||||
.macro if_dont_have_move, target, move, address
|
||||
.byte 0x40
|
||||
.byte \target
|
||||
.2byte \move
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_move_effect target, effect, address
|
||||
.byte 0x41
|
||||
.byte \target
|
||||
.byte \effect
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_not_move_effect target, effect, address
|
||||
.byte 0x42
|
||||
.byte \target
|
||||
.byte \effect
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_last_move_did_damage target, byte, address
|
||||
.byte 0x43
|
||||
.byte \target
|
||||
.byte \byte
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_encored target, address
|
||||
.byte 0x44
|
||||
.byte \target
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro flee
|
||||
.byte 0x45
|
||||
.endm
|
||||
|
||||
.macro if_random_100 address
|
||||
.byte 0x46
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro watch
|
||||
.byte 0x47
|
||||
.endm
|
||||
|
||||
.macro get_hold_effect target
|
||||
.byte 0x48
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
.macro get_gender target
|
||||
.byte 0x49
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
.macro is_first_turn target
|
||||
.byte 0x4a
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
.macro get_stockpile_count target
|
||||
.byte 0x4b
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
.macro is_double_battle
|
||||
.byte 0x4c
|
||||
.endm
|
||||
|
||||
.macro get_item target
|
||||
.byte 0x4d
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
.macro get_move_type_from_result
|
||||
.byte 0x4e
|
||||
.endm
|
||||
|
||||
.macro get_move_power_from_result
|
||||
.byte 0x4f
|
||||
.endm
|
||||
|
||||
.macro get_move_effect_from_result
|
||||
.byte 0x50
|
||||
.endm
|
||||
|
||||
.macro get_protect_count target
|
||||
.byte 0x51
|
||||
.byte \target
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_52
|
||||
.byte 0x52
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_53
|
||||
.byte 0x53
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_54
|
||||
.byte 0x54
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_55
|
||||
.byte 0x55
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_56
|
||||
.byte 0x56
|
||||
.endm
|
||||
|
||||
@ nullsub
|
||||
.macro ai_57
|
||||
.byte 0x57
|
||||
.endm
|
||||
|
||||
@ unused
|
||||
.macro call address
|
||||
.byte 0x58
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro jump address
|
||||
.byte 0x59
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro end
|
||||
.byte 0x5a
|
||||
.endm
|
||||
|
||||
.macro if_level_cond cond, address
|
||||
.byte 0x5b
|
||||
.byte \cond
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_user_higher_level address
|
||||
if_level_cond 0, \address
|
||||
.endm
|
||||
|
||||
.macro if_target_higher_level address
|
||||
if_level_cond 1, \address
|
||||
.endm
|
||||
|
||||
.macro if_equal_levels address
|
||||
if_level_cond 2, \address
|
||||
.endm
|
||||
|
||||
@ unused
|
||||
.macro if_taunted address
|
||||
.byte 0x5c
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro if_not_taunted address
|
||||
.byte 0x5d
|
||||
.4byte \address
|
||||
.endm
|
||||
@@ -0,0 +1,266 @@
|
||||
.macro loadsprite id
|
||||
.byte 0x00
|
||||
.2byte \id
|
||||
.endm
|
||||
|
||||
.macro unloadsprite id
|
||||
.byte 0x01
|
||||
.2byte \id
|
||||
.endm
|
||||
|
||||
.macro sprite template, priority, argv:vararg
|
||||
.byte 0x02
|
||||
.4byte \template
|
||||
.byte \priority
|
||||
.byte (.Lsprite_\@_2 - .Lsprite_\@_1) / 2
|
||||
.Lsprite_\@_1:
|
||||
.2byte \argv
|
||||
.Lsprite_\@_2:
|
||||
.endm
|
||||
|
||||
.macro createtask addr, priority, argv:vararg
|
||||
.byte 0x03
|
||||
.4byte \addr
|
||||
.byte \priority
|
||||
.byte (.Lcreatetask_\@_2 - .Lcreatetask_\@_1) / 2
|
||||
.Lcreatetask_\@_1:
|
||||
.2byte \argv
|
||||
.Lcreatetask_\@_2:
|
||||
.endm
|
||||
|
||||
.macro pause delay
|
||||
.byte 0x04
|
||||
.byte \delay
|
||||
.endm
|
||||
|
||||
.macro wait
|
||||
.byte 0x05
|
||||
.endm
|
||||
|
||||
.macro hang1
|
||||
.byte 0x06
|
||||
.endm
|
||||
|
||||
.macro hang2
|
||||
.byte 0x07
|
||||
.endm
|
||||
|
||||
.macro end
|
||||
.byte 0x08
|
||||
.endm
|
||||
|
||||
.macro playse id
|
||||
.byte 0x09
|
||||
.2byte \id
|
||||
.endm
|
||||
|
||||
.macro monbg which
|
||||
.byte 0x0A
|
||||
.byte \which
|
||||
.endm
|
||||
|
||||
.macro clearmonbg which
|
||||
.byte 0x0B
|
||||
.byte \which
|
||||
.endm
|
||||
|
||||
.macro setalpha eva, evb
|
||||
.byte 0x0C
|
||||
.2byte ((\evb) << 8) | (\eva)
|
||||
.endm
|
||||
|
||||
.macro blendoff
|
||||
.byte 0x0D
|
||||
.endm
|
||||
|
||||
.macro call addr
|
||||
.byte 0x0E
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro ret
|
||||
.byte 0x0F
|
||||
.endm
|
||||
|
||||
.macro setvar var_num, value
|
||||
.byte 0x10
|
||||
.byte \var_num
|
||||
.2byte \value
|
||||
.endm
|
||||
|
||||
.macro ifelse addr1, addr2
|
||||
.byte 0x11
|
||||
.4byte \addr1
|
||||
.4byte \addr2
|
||||
.endm
|
||||
|
||||
.macro jumpif cond, addr
|
||||
.byte 0x12
|
||||
.byte \cond
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro jump addr
|
||||
.byte 0x13
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro fadetobg id
|
||||
.byte 0x14
|
||||
.byte \id
|
||||
.endm
|
||||
|
||||
.macro restorebg
|
||||
.byte 0x15
|
||||
.endm
|
||||
|
||||
.macro waitbgfadeout
|
||||
.byte 0x16
|
||||
.endm
|
||||
|
||||
.macro waitbgfadein
|
||||
.byte 0x17
|
||||
.endm
|
||||
|
||||
.macro changebg id
|
||||
.byte 0x18
|
||||
.byte \id
|
||||
.endm
|
||||
|
||||
.macro panse_19 id, pan
|
||||
.byte 0x19
|
||||
.2byte \id
|
||||
.byte \pan
|
||||
.endm
|
||||
|
||||
.macro setpan pan
|
||||
.byte 0x1A
|
||||
.byte \pan
|
||||
.endm
|
||||
|
||||
.macro panse_1B id, pan_start, pan_end, step, delay
|
||||
.byte 0x1B
|
||||
.2byte \id
|
||||
.byte \pan_start
|
||||
.byte \pan_end
|
||||
.byte \step
|
||||
.byte \delay
|
||||
.endm
|
||||
|
||||
.macro panse_1C id, pan, delay, count
|
||||
.byte 0x1C
|
||||
.2byte \id
|
||||
.byte \pan
|
||||
.byte \delay
|
||||
.byte \count
|
||||
.endm
|
||||
|
||||
.macro panse_1D id, pan, count
|
||||
.byte 0x1D
|
||||
.2byte \id
|
||||
.byte \pan
|
||||
.byte \count
|
||||
.endm
|
||||
|
||||
.macro setbldcnt bldcnt
|
||||
.byte 0x1E
|
||||
.2byte \bldcnt
|
||||
.endm
|
||||
|
||||
.macro createtask_1F addr, argv:vararg
|
||||
.byte 0x1F
|
||||
.4byte \addr
|
||||
.byte (.Lcreatetask_1F_\@_2 - .Lcreatetask_1F_\@_1) / 2
|
||||
.Lcreatetask_1F_\@_1:
|
||||
.2byte \argv
|
||||
.Lcreatetask_1F_\@_2:
|
||||
.endm
|
||||
|
||||
.macro waitsound
|
||||
.byte 0x20
|
||||
.endm
|
||||
|
||||
.macro jumpvareq var_num, value, addr
|
||||
.byte 0x21
|
||||
.byte \var_num
|
||||
.2byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro monbg_22 unk
|
||||
.byte 0x22
|
||||
.byte \unk
|
||||
.endm
|
||||
|
||||
.macro clearmonbg_23 unk
|
||||
.byte 0x23
|
||||
.byte \unk
|
||||
.endm
|
||||
|
||||
.macro jumpunkcond addr
|
||||
.byte 0x24
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro fadetobg_25 a, b, c
|
||||
.byte 0x25
|
||||
.byte \a
|
||||
.byte \b
|
||||
.byte \c
|
||||
.endm
|
||||
|
||||
.macro panse_26 id, pan_start, pan_end, step, delay
|
||||
.byte 0x26
|
||||
.2byte \id
|
||||
.byte \pan_start
|
||||
.byte \pan_end
|
||||
.byte \step
|
||||
.byte \delay
|
||||
.endm
|
||||
|
||||
.macro panse_27 id, pan_start, pan_end, step, delay
|
||||
.byte 0x27
|
||||
.2byte \id
|
||||
.byte \pan_start
|
||||
.byte \pan_end
|
||||
.byte \step
|
||||
.byte \delay
|
||||
.endm
|
||||
|
||||
.macro monbgprio_28 unk
|
||||
.byte 0x28
|
||||
.byte \unk
|
||||
.endm
|
||||
|
||||
.macro monbgprio_29
|
||||
.byte 0x29
|
||||
.endm
|
||||
|
||||
.macro monbgprio_2A unk
|
||||
.byte 0x2A
|
||||
.byte \unk
|
||||
.endm
|
||||
|
||||
.macro invisible side
|
||||
.byte 0x2B
|
||||
.byte \side
|
||||
.endm
|
||||
|
||||
.macro visible side
|
||||
.byte 0x2C
|
||||
.byte \side
|
||||
.endm
|
||||
|
||||
.macro doublebattle_2D unk
|
||||
.byte 0x2D
|
||||
.byte \unk
|
||||
.endm
|
||||
|
||||
.macro doublebattle_2E unk
|
||||
.byte 0x2E
|
||||
.byte \unk
|
||||
.endm
|
||||
|
||||
.macro stopsound
|
||||
.byte 0x2F
|
||||
.endm
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,506 @@
|
||||
@ Add a positive/negative value to the score of the move being evaluated.
|
||||
|
||||
.macro score score
|
||||
.byte 0x00
|
||||
.byte \score
|
||||
.endm
|
||||
|
||||
@ turn (AKA "Appeal No.")
|
||||
|
||||
.macro get_turn
|
||||
.byte 0x01
|
||||
.endm
|
||||
|
||||
.macro if_turn_less_than param, addr
|
||||
.byte 0x02
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_turn_more_than param, addr
|
||||
.byte 0x03
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_turn_eq param, addr
|
||||
.byte 0x04
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_turn_not_eq param, addr
|
||||
.byte 0x05
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ audience excitement
|
||||
|
||||
.macro get_excitement
|
||||
.byte 0x06
|
||||
.endm
|
||||
|
||||
.macro if_excitement_less_than param, addr
|
||||
.byte 0x07
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_excitement_more_than param, addr
|
||||
.byte 0x08
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_excitement_eq param, addr
|
||||
.byte 0x09
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_excitement_not_eq param, addr
|
||||
.byte 0x0A
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ the order that the user goes in the current turn
|
||||
|
||||
.macro get_user_order
|
||||
.byte 0x0B
|
||||
.endm
|
||||
|
||||
.macro if_user_order_less_than param addr
|
||||
.byte 0x0C
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_user_order_more_than param addr
|
||||
.byte 0x0D
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_user_order_eq param addr
|
||||
.byte 0x0E
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_user_order_not_eq param addr
|
||||
.byte 0x0F
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ user condition
|
||||
|
||||
.macro get_user_condition
|
||||
.byte 0x10
|
||||
.endm
|
||||
|
||||
.macro if_user_condition_less_than param, addr
|
||||
.byte 0x11
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_user_condition_more_than param, addr
|
||||
.byte 0x12
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_user_condition_eq param, addr
|
||||
.byte 0x13
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_user_condition_not_eq param, addr
|
||||
.byte 0x14
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ 15
|
||||
@ 16
|
||||
@ 17
|
||||
@ 18
|
||||
@ 19
|
||||
@ 1A
|
||||
@ 1B
|
||||
@ 1C
|
||||
@ 1D
|
||||
@ 1E
|
||||
|
||||
@ contest type
|
||||
|
||||
.macro get_contest_type
|
||||
.byte 0x1F
|
||||
.endm
|
||||
|
||||
.macro if_contest_type_eq param, addr
|
||||
.byte 0x20
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_contest_type_not_eq param, addr
|
||||
.byte 0x21
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ move excitement (change in excitement due to move)
|
||||
|
||||
.macro get_move_excitement
|
||||
.byte 0x22
|
||||
.endm
|
||||
|
||||
.macro if_move_excitement_less_than param, addr
|
||||
.byte 0x23
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_move_excitement_more_than param, addr
|
||||
.byte 0x24
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_move_excitement_eq param, addr
|
||||
.byte 0x25
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_move_excitement_not_eq param, addr
|
||||
.byte 0x26
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ move effect
|
||||
|
||||
.macro get_effect
|
||||
.byte 0x27
|
||||
.endm
|
||||
|
||||
.macro if_effect_eq param, addr
|
||||
.byte 0x28
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_effect_not_eq param, addr
|
||||
.byte 0x29
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ move effect type
|
||||
|
||||
.macro get_effect_type
|
||||
.byte 0x2A
|
||||
.endm
|
||||
|
||||
.macro if_effect_type_eq param, addr
|
||||
.byte 0x2B
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_effect_type_not_eq param, addr
|
||||
.byte 0x2C
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ whether the current move is the most appealing in the user's moveset
|
||||
|
||||
.macro check_most_appealing_move
|
||||
.byte 0x2D
|
||||
.endm
|
||||
|
||||
.macro if_most_appealing_move addr
|
||||
.byte 0x2E
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ 2F
|
||||
@ 30
|
||||
@ 31
|
||||
@ 32
|
||||
@ 33
|
||||
@ 34
|
||||
@ 35
|
||||
@ 36
|
||||
@ 37
|
||||
@ 38
|
||||
@ 39
|
||||
@ 3A
|
||||
|
||||
@ number of times current move has been used
|
||||
|
||||
.macro get_move_used_count
|
||||
.byte 0x3B
|
||||
.endm
|
||||
|
||||
.macro if_move_used_count_less_than param, addr
|
||||
.byte 0x3C
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_move_used_count_more_than param, addr
|
||||
.byte 0x3D
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_move_used_count_eq param, addr
|
||||
.byte 0x3E
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_move_used_count_not_eq param, addr
|
||||
.byte 0x3F
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ whether the current move is a combo starter (with another move in the moveset)
|
||||
|
||||
.macro check_combo_starter
|
||||
.byte 0x40
|
||||
.endm
|
||||
|
||||
.macro if_combo_starter addr
|
||||
.byte 0x41
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_not_combo_starter addr
|
||||
.byte 0x42
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ whether the current move is a combo finisher (with another move in the moveset)
|
||||
|
||||
.macro check_combo_finisher
|
||||
.byte 0x43
|
||||
.endm
|
||||
|
||||
.macro if_combo_finisher addr
|
||||
.byte 0x44
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_not_combo_finisher addr
|
||||
.byte 0x45
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ whether the current move would finish a combo
|
||||
|
||||
.macro check_would_finish_combo
|
||||
.byte 0x46
|
||||
.endm
|
||||
|
||||
.macro if_would_finish_combo addr
|
||||
.byte 0x47
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_would_not_finish_combo addr
|
||||
.byte 0x48
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ condition of mon (indexed by order)
|
||||
|
||||
.macro get_condition mon
|
||||
.byte 0x49
|
||||
.byte \mon
|
||||
.endm
|
||||
|
||||
.macro if_condition_less_than mon, value, addr
|
||||
.byte 0x4A
|
||||
.byte \mon
|
||||
.byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_condition_more_than mon, value, addr
|
||||
.byte 0x4B
|
||||
.byte \mon
|
||||
.byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_condition_eq mon, value, addr
|
||||
.byte 0x4C
|
||||
.byte \mon
|
||||
.byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_condition_not_eq mon, value, addr
|
||||
.byte 0x4D
|
||||
.byte \mon
|
||||
.byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ whether the mon used a combo starter move
|
||||
@ Even though this value is always 1 or 0 (i.e. TRUE/FALSE),
|
||||
@ there are less-than and greater-than comparison operations for some reason.
|
||||
|
||||
.macro get_used_combo_starter mon
|
||||
.byte 0x4E
|
||||
.byte \mon
|
||||
.endm
|
||||
|
||||
.macro if_used_combo_starter_less_than mon, value, addr
|
||||
.byte 0x4F
|
||||
.byte \mon
|
||||
.byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_used_combo_starter_more_than mon, value, addr
|
||||
.byte 0x50
|
||||
.byte \mon
|
||||
.byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
|
||||
.macro if_used_combo_starter_eq mon, value, addr
|
||||
.byte 0x51
|
||||
.byte \mon
|
||||
.byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_used_combo_starter_not_eq mon, value, addr
|
||||
.byte 0x52
|
||||
.byte \mon
|
||||
.byte \value
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ whether the mon can make an appeal
|
||||
|
||||
.macro check_can_participate mon
|
||||
.byte 0x53
|
||||
.byte \mon
|
||||
.endm
|
||||
|
||||
.macro if_can_participate mon, addr
|
||||
.byte 0x54
|
||||
.byte \mon
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_cannot_participate mon, addr
|
||||
.byte 0x55
|
||||
.byte \mon
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ 56
|
||||
@ 57
|
||||
|
||||
.macro contest_58 param addr
|
||||
.byte 0x58
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ 59
|
||||
@ 5A
|
||||
@ 5B
|
||||
@ 5C
|
||||
@ 5D
|
||||
@ 5E
|
||||
@ 5F
|
||||
@ 60
|
||||
@ 61
|
||||
@ 62
|
||||
@ 63
|
||||
@ 64
|
||||
@ 65
|
||||
@ 66
|
||||
@ 67
|
||||
@ 68
|
||||
@ 69
|
||||
@ 6A
|
||||
@ 6B
|
||||
@ 6C
|
||||
@ 6D
|
||||
@ 6E
|
||||
@ 6F
|
||||
@ 70
|
||||
@ 71
|
||||
@ 72
|
||||
@ 73
|
||||
@ 74
|
||||
@ 75
|
||||
@ 76
|
||||
@ 77
|
||||
@ 78
|
||||
@ 79
|
||||
@ 7A
|
||||
@ 7B
|
||||
@ 7C
|
||||
|
||||
.macro if_random param addr
|
||||
.byte 0x7D
|
||||
.byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ 7E
|
||||
|
||||
.macro jump addr
|
||||
.byte 0x7F
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro call addr
|
||||
.byte 0x80
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro end
|
||||
.byte 0x81
|
||||
.endm
|
||||
|
||||
.macro check_user_has_exciting_move
|
||||
.byte 0x82
|
||||
.endm
|
||||
|
||||
.macro if_user_has_exciting_move addr
|
||||
.byte 0x83
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
.macro if_user_doesnt_have_exciting_move addr
|
||||
.byte 0x84
|
||||
.4byte \addr
|
||||
.endm
|
||||
|
||||
@ 85
|
||||
@ 86
|
||||
|
||||
.macro if_effect_in_user_moveset param addr
|
||||
.byte 0x87
|
||||
.2byte \param
|
||||
.4byte \addr
|
||||
.endm
|
||||
@@ -0,0 +1,8 @@
|
||||
|
||||
.macro ec_duplicates count
|
||||
.2byte 0xff00 + \count
|
||||
.endm
|
||||
|
||||
.macro ec_words_by_letter label
|
||||
.2byte (gEasyChatWordsByLetter_\label - gEasyChatWordsAlphabetized) / 2
|
||||
.endm
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,42 @@
|
||||
.macro loadtiles address
|
||||
.byte 0
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro loadfadedpal address
|
||||
.byte 1
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro loadpal address
|
||||
.byte 2
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro callnative address
|
||||
.byte 3
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro end
|
||||
.byte 4
|
||||
.endm
|
||||
|
||||
.macro loadgfx_callnative tiles_address, palette_address, function_address
|
||||
.byte 5
|
||||
.4byte \tiles_address
|
||||
.4byte \palette_address
|
||||
.4byte \function_address
|
||||
.endm
|
||||
|
||||
.macro loadtiles_callnative tiles_address, function_address
|
||||
.byte 6
|
||||
.4byte \tiles_address
|
||||
.4byte \function_address
|
||||
.endm
|
||||
|
||||
.macro loadfadedpal_callnative palette_address, function_address
|
||||
.byte 7
|
||||
.4byte \palette_address
|
||||
.4byte \function_address
|
||||
.endm
|
||||
@@ -0,0 +1,29 @@
|
||||
.macro arm_func_start name
|
||||
.align 2, 0
|
||||
.global \name
|
||||
.arm
|
||||
.type \name, function
|
||||
.endm
|
||||
|
||||
.macro arm_func_end name
|
||||
.size \name, .-\name
|
||||
.endm
|
||||
|
||||
.macro thumb_func_start name
|
||||
.align 2, 0
|
||||
.global \name
|
||||
.thumb
|
||||
.thumb_func
|
||||
.type \name, function
|
||||
.endm
|
||||
|
||||
.macro non_word_aligned_thumb_func_start name
|
||||
.global \name
|
||||
.thumb
|
||||
.thumb_func
|
||||
.type \name, function
|
||||
.endm
|
||||
|
||||
.macro thumb_func_end name
|
||||
.size \name, .-\name
|
||||
.endm
|
||||
@@ -0,0 +1,13 @@
|
||||
.macro song label, music_player, unknown
|
||||
.4byte \label
|
||||
.2byte \music_player
|
||||
.2byte \unknown
|
||||
.endm
|
||||
|
||||
.macro music_player info_struct, track_struct, unknown_1, unknown_2
|
||||
.4byte \info_struct
|
||||
.4byte \track_struct
|
||||
.byte \unknown_1
|
||||
.space 1
|
||||
.2byte \unknown_2
|
||||
.endm
|
||||
@@ -0,0 +1,84 @@
|
||||
.macro map map_id
|
||||
.byte \map_id >> 8 @ map group
|
||||
.byte \map_id & 0xFF @ map num
|
||||
.endm
|
||||
|
||||
.macro map_script type, address
|
||||
.byte \type
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro map_script_2 word1, word2, address
|
||||
.2byte \word1
|
||||
.2byte \word2
|
||||
.4byte \address
|
||||
.endm
|
||||
|
||||
.macro object_event byte1, word1, byte2, byte3, byte4, byte5, byte6, byte7, byte8, byte9, byte10, byte11, byte12, byte13, byte14, script, word2, byte15, byte16
|
||||
.byte \byte1
|
||||
.2byte \word1
|
||||
.byte \byte2, \byte3, \byte4, \byte5, \byte6, \byte7, \byte8, \byte9, \byte10, \byte11, \byte12, \byte13, \byte14
|
||||
.4byte \script
|
||||
.2byte \word2
|
||||
.byte \byte15, \byte16
|
||||
inc _num_npcs
|
||||
.endm
|
||||
|
||||
.macro warp_def x, y, byte, warp, map_id
|
||||
.2byte \x, \y
|
||||
.byte \byte, \warp
|
||||
.byte \map_id & 0xFF @ map num
|
||||
.byte \map_id >> 8 @ map group
|
||||
inc _num_warps
|
||||
.endm
|
||||
|
||||
.macro coord_event x, y, byte1, byte2, word1, word2, word3, script
|
||||
.2byte \x, \y
|
||||
.byte \byte1, \byte2
|
||||
.2byte \word1, \word2, \word3
|
||||
.4byte \script
|
||||
inc _num_traps
|
||||
.endm
|
||||
|
||||
.macro bg_event x, y, byte, kind, word, arg6, arg7, arg8
|
||||
.2byte \x, \y
|
||||
.byte \byte, \kind
|
||||
.2byte \word
|
||||
.if \kind < 5
|
||||
.4byte \arg6
|
||||
.else
|
||||
.2byte \arg6
|
||||
.byte \arg7, \arg8
|
||||
.endif
|
||||
inc _num_signs
|
||||
.endm
|
||||
|
||||
.macro map_events npcs, warps, traps, signs
|
||||
.byte _num_npcs, _num_warps, _num_traps, _num_signs
|
||||
.4byte \npcs, \warps, \traps, \signs
|
||||
reset_map_events
|
||||
.endm
|
||||
|
||||
.macro reset_map_events
|
||||
.set _num_npcs, 0
|
||||
.set _num_warps, 0
|
||||
.set _num_traps, 0
|
||||
.set _num_signs, 0
|
||||
.endm
|
||||
|
||||
reset_map_events
|
||||
|
||||
|
||||
.equiv connection_down, 1
|
||||
.equiv connection_up, 2
|
||||
.equiv connection_left, 3
|
||||
.equiv connection_right, 4
|
||||
.equiv connection_dive, 5
|
||||
.equiv connection_emerge, 6
|
||||
|
||||
.macro connection direction, offset, map, filler
|
||||
.4byte connection_\direction
|
||||
.4byte \offset
|
||||
map \map
|
||||
.space 2
|
||||
.endm
|
||||
@@ -0,0 +1,120 @@
|
||||
.macro create_movement name
|
||||
enum _\name
|
||||
.macro \name
|
||||
.byte _\name
|
||||
.endm
|
||||
.endm
|
||||
|
||||
enum_start
|
||||
create_movement step_00
|
||||
create_movement step_01
|
||||
create_movement step_02
|
||||
create_movement step_03
|
||||
create_movement slow_step_down
|
||||
create_movement slow_step_up
|
||||
create_movement slow_step_left
|
||||
create_movement slow_step_right
|
||||
create_movement step_down
|
||||
create_movement step_up
|
||||
create_movement step_left
|
||||
create_movement step_right
|
||||
create_movement fast_step_down
|
||||
create_movement fast_step_up
|
||||
create_movement fast_step_left
|
||||
create_movement fast_step_right
|
||||
create_movement step_10
|
||||
create_movement step_11
|
||||
create_movement step_12
|
||||
create_movement step_13
|
||||
create_movement step_14
|
||||
create_movement step_15
|
||||
create_movement step_16
|
||||
create_movement step_17
|
||||
create_movement step_18
|
||||
create_movement step_19
|
||||
create_movement step_1a
|
||||
create_movement step_1b
|
||||
create_movement step_1c
|
||||
create_movement step_1d
|
||||
create_movement step_1e
|
||||
create_movement step_1f
|
||||
create_movement step_20
|
||||
create_movement step_21
|
||||
create_movement step_22
|
||||
create_movement step_23
|
||||
create_movement step_24
|
||||
create_movement step_25
|
||||
create_movement step_26
|
||||
create_movement step_27
|
||||
create_movement step_28
|
||||
create_movement step_29
|
||||
create_movement step_2a
|
||||
create_movement step_2b
|
||||
create_movement step_2c
|
||||
create_movement step_2d
|
||||
create_movement step_2e
|
||||
create_movement step_2f
|
||||
create_movement step_30
|
||||
create_movement step_31
|
||||
create_movement step_32
|
||||
create_movement step_33
|
||||
create_movement step_34
|
||||
create_movement step_35
|
||||
create_movement step_36
|
||||
create_movement step_37
|
||||
create_movement step_38
|
||||
create_movement step_39
|
||||
create_movement step_3a
|
||||
create_movement step_3b
|
||||
create_movement step_3c
|
||||
create_movement step_3d
|
||||
create_movement step_3e
|
||||
create_movement step_3f
|
||||
create_movement step_40
|
||||
create_movement step_41
|
||||
create_movement step_42
|
||||
create_movement step_43
|
||||
create_movement step_44
|
||||
create_movement step_45
|
||||
create_movement step_46
|
||||
create_movement step_47
|
||||
create_movement step_48
|
||||
create_movement step_49
|
||||
create_movement step_4a
|
||||
create_movement step_4b
|
||||
create_movement step_4c
|
||||
create_movement step_4d
|
||||
create_movement step_4e
|
||||
create_movement step_4f
|
||||
create_movement step_50
|
||||
create_movement step_51
|
||||
create_movement step_52
|
||||
create_movement step_53
|
||||
create_movement step_54
|
||||
create_movement step_55
|
||||
create_movement step_56
|
||||
create_movement step_57
|
||||
create_movement step_58
|
||||
create_movement step_59
|
||||
create_movement step_5a
|
||||
create_movement step_5b
|
||||
create_movement step_5c
|
||||
create_movement step_5d
|
||||
create_movement step_5e
|
||||
create_movement step_5f
|
||||
create_movement step_60
|
||||
create_movement step_61
|
||||
create_movement step_62
|
||||
create_movement step_63
|
||||
create_movement step_64
|
||||
create_movement step_65
|
||||
|
||||
enum_start 0x91
|
||||
create_movement step_91
|
||||
create_movement step_92
|
||||
|
||||
enum_start 0x96
|
||||
create_movement step_96
|
||||
|
||||
enum_start 0xfe
|
||||
create_movement step_end
|
||||
@@ -0,0 +1,125 @@
|
||||
.macro voice_directsound base_midi_key, pan, sample_data_pointer, attack, decay, sustain, release
|
||||
.byte 0
|
||||
_voice_directsound \base_midi_key, \pan, \sample_data_pointer, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro voice_directsound_no_resample base_midi_key, pan, sample_data_pointer, attack, decay, sustain, release
|
||||
.byte 8
|
||||
_voice_directsound \base_midi_key, \pan, \sample_data_pointer, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro voice_directsound_alt base_midi_key, pan, sample_data_pointer, attack, decay, sustain, release
|
||||
.byte 16
|
||||
_voice_directsound \base_midi_key, \pan, \sample_data_pointer, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro _voice_directsound base_midi_key, pan, sample_data_pointer, attack, decay, sustain, release
|
||||
.byte \base_midi_key
|
||||
.byte 0
|
||||
.if \pan != 0
|
||||
.byte (0x80 | \pan)
|
||||
.else
|
||||
.byte 0
|
||||
.endif
|
||||
.4byte \sample_data_pointer
|
||||
.byte \attack
|
||||
.byte \decay
|
||||
.byte \sustain
|
||||
.byte \release
|
||||
.endm
|
||||
|
||||
.macro voice_square_1 sweep, duty_cycle, attack, decay, sustain, release
|
||||
_voice_square_1 1, \sweep, \duty_cycle, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro voice_square_1_alt sweep, duty_cycle, attack, decay, sustain, release
|
||||
_voice_square_1 9, \sweep, \duty_cycle, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro _voice_square_1 type, sweep, duty_cycle, attack, decay, sustain, release
|
||||
.byte \type, 60, 0
|
||||
.byte \sweep
|
||||
.byte (\duty_cycle & 0x3)
|
||||
.byte 0, 0, 0
|
||||
.byte (\attack & 0x7)
|
||||
.byte (\decay & 0x7)
|
||||
.byte (\sustain & 0xF)
|
||||
.byte (\release & 0x7)
|
||||
.endm
|
||||
|
||||
.macro voice_square_2 duty_cycle, attack, decay, sustain, release
|
||||
_voice_square_2 2, \duty_cycle, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro voice_square_2_alt duty_cycle, attack, decay, sustain, release
|
||||
_voice_square_2 10, \duty_cycle, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro _voice_square_2 type, duty_cycle, attack, decay, sustain, release
|
||||
.byte \type, 60, 0, 0
|
||||
.byte (\duty_cycle & 0x3)
|
||||
.byte 0, 0, 0
|
||||
.byte (\attack & 0x7)
|
||||
.byte (\decay & 0x7)
|
||||
.byte (\sustain & 0xF)
|
||||
.byte (\release & 0x7)
|
||||
.endm
|
||||
|
||||
.macro voice_programmable_wave wave_samples_pointer, attack, decay, sustain, release
|
||||
_voice_programmable_wave 3, \wave_samples_pointer, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro voice_programmable_wave_alt wave_samples_pointer, attack, decay, sustain, release
|
||||
_voice_programmable_wave 11, \wave_samples_pointer, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro _voice_programmable_wave type, wave_samples_pointer, attack, decay, sustain, release
|
||||
.byte \type, 60, 0, 0
|
||||
.4byte \wave_samples_pointer
|
||||
.byte (\attack & 0x7)
|
||||
.byte (\decay & 0x7)
|
||||
.byte (\sustain & 0xF)
|
||||
.byte (\release & 0x7)
|
||||
.endm
|
||||
|
||||
.macro voice_noise period, attack, decay, sustain, release
|
||||
_voice_noise 4, \period, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro voice_noise_alt period, attack, decay, sustain, release
|
||||
_voice_noise 12, \period, \attack, \decay, \sustain, \release
|
||||
.endm
|
||||
|
||||
.macro _voice_noise type, period, attack, decay, sustain, release
|
||||
.byte \type, 60, 0, 0
|
||||
.byte (\period & 0x1)
|
||||
.byte 0, 0, 0
|
||||
.byte (\attack & 0x7)
|
||||
.byte (\decay & 0x7)
|
||||
.byte (\sustain & 0xF)
|
||||
.byte (\release & 0x7)
|
||||
.endm
|
||||
|
||||
.macro voice_keysplit voice_group_pointer, keysplit_table_pointer
|
||||
.byte 0x40, 0, 0, 0
|
||||
.4byte \voice_group_pointer
|
||||
.4byte \keysplit_table_pointer
|
||||
.endm
|
||||
|
||||
.macro voice_keysplit_all voice_group_pointer
|
||||
.byte 0x80, 0, 0, 0
|
||||
.4byte \voice_group_pointer
|
||||
.4byte 0
|
||||
.endm
|
||||
|
||||
.macro cry sample
|
||||
.byte 0x20, 60, 0, 0
|
||||
.4byte \sample
|
||||
.byte 0xff, 0, 0xff, 0
|
||||
.endm
|
||||
|
||||
.macro cry2 sample
|
||||
.byte 0x30, 60, 0, 0
|
||||
.4byte \sample
|
||||
.byte 0xff, 0, 0xff, 0
|
||||
.endm
|
||||
@@ -0,0 +1,57 @@
|
||||
.macro pokedex_entry pokemon_name, height, weight, pokemon_scale, pokemon_offset, trainer_scale, trainer_offset
|
||||
.2byte \height @ in decimeters
|
||||
.2byte \weight @ in hectograms
|
||||
.4byte DexDescription_\pokemon_name\()_1
|
||||
.4byte DexDescription_\pokemon_name\()_2
|
||||
.2byte 0 @ unused
|
||||
.2byte \pokemon_scale
|
||||
.2byte \pokemon_offset
|
||||
.2byte \trainer_scale
|
||||
.2byte \trainer_offset
|
||||
.2byte 0 @ padding
|
||||
.endm
|
||||
|
||||
.macro base_stats hp, attack, defense, speed, sp_attack, sp_defense
|
||||
.byte \hp
|
||||
.byte \attack
|
||||
.byte \defense
|
||||
.byte \speed
|
||||
.byte \sp_attack
|
||||
.byte \sp_defense
|
||||
.endm
|
||||
|
||||
.macro ev_yield hp, attack, defense, speed, sp_attack, sp_defense
|
||||
.2byte (\sp_defense << 10) | (\sp_attack << 8) | (\speed << 6) | (\defense << 4) | (\attack << 2) | \hp
|
||||
.endm
|
||||
|
||||
.macro level_up_move level, move
|
||||
.2byte (\level << 9) | \move
|
||||
.endm
|
||||
|
||||
.macro evo_entry method, parameter, target_species
|
||||
.2byte \method
|
||||
.2byte \parameter
|
||||
.2byte \target_species
|
||||
.2byte 0 @ padding
|
||||
.endm
|
||||
|
||||
.macro empty_evo_entries count
|
||||
.fill 8 * \count, 1, 0
|
||||
.endm
|
||||
|
||||
.macro egg_moves_begin species
|
||||
.2byte 20000 + \species
|
||||
.endm
|
||||
|
||||
@ If the min level equals the max level, only one level argument is needed.
|
||||
.macro wild_mon species, min_level, max_level
|
||||
.byte \min_level
|
||||
|
||||
.ifb \max_level
|
||||
.byte \min_level
|
||||
.else
|
||||
.byte \max_level
|
||||
.endif
|
||||
|
||||
.2byte SPECIES_\species
|
||||
.endm
|
||||
@@ -0,0 +1,490 @@
|
||||
.set PSR_USR_MODE, 0x00000010
|
||||
.set PSR_FIQ_MODE, 0x00000011
|
||||
.set PSR_IRQ_MODE, 0x00000012
|
||||
.set PSR_SVC_MODE, 0x00000013
|
||||
.set PSR_ABT_MODE, 0x00000017
|
||||
.set PSR_UND_MODE, 0x0000001b
|
||||
.set PSR_SYS_MODE, 0x0000001f
|
||||
.set PSR_MODE_MASK, 0x0000001f
|
||||
.set PSR_T_BIT, 0x00000020
|
||||
.set PSR_F_BIT, 0x00000040
|
||||
.set PSR_I_BIT, 0x00000080
|
||||
|
||||
.set EWRAM_START, 0x02000000
|
||||
.set EWRAM_END, EWRAM_START + 0x40000
|
||||
.set IWRAM_START, 0x03000000
|
||||
.set IWRAM_END, IWRAM_START + 0x8000
|
||||
|
||||
.set PLTT, 0x5000000
|
||||
.set BG_PLTT, PLTT
|
||||
.set OBJ_PLTT, PLTT + 0x200
|
||||
|
||||
.set VRAM, 0x6000000
|
||||
.set BG_VRAM, VRAM
|
||||
.set OBJ_VRAM0, VRAM + 0x10000 @ text-mode BG
|
||||
.set OBJ_VRAM1, VRAM + 0x14000 @ bitmap-mode BG
|
||||
|
||||
.set OAM, 0x7000000
|
||||
|
||||
.set SOUND_INFO_PTR, 0x3007FF0
|
||||
.set INTR_CHECK, 0x3007FF8
|
||||
.set INTR_VECTOR, 0x3007FFC
|
||||
|
||||
.set INTR_FLAG_VBLANK, 1 << 0
|
||||
.set INTR_FLAG_HBLANK, 1 << 1
|
||||
.set INTR_FLAG_VCOUNT, 1 << 2
|
||||
.set INTR_FLAG_TIMER0, 1 << 3
|
||||
.set INTR_FLAG_TIMER1, 1 << 4
|
||||
.set INTR_FLAG_TIMER2, 1 << 5
|
||||
.set INTR_FLAG_TIMER3, 1 << 6
|
||||
.set INTR_FLAG_SERIAL, 1 << 7
|
||||
.set INTR_FLAG_DMA0, 1 << 8
|
||||
.set INTR_FLAG_DMA1, 1 << 9
|
||||
.set INTR_FLAG_DMA2, 1 << 10
|
||||
.set INTR_FLAG_DMA3, 1 << 11
|
||||
.set INTR_FLAG_KEYPAD, 1 << 12
|
||||
.set INTR_FLAG_GAMEPAK, 1 << 13
|
||||
|
||||
.set VCOUNT_VBLANK, 160
|
||||
.set TOTAL_SCANLINES, 228
|
||||
|
||||
.set REG_BASE, 0x4000000 @ I/O register base address
|
||||
|
||||
@ I/O register offsets
|
||||
.set OFFSET_REG_DISPCNT, 0x0
|
||||
.set OFFSET_REG_DISPSTAT, 0x4
|
||||
.set OFFSET_REG_VCOUNT, 0x6
|
||||
.set OFFSET_REG_BG0CNT, 0x8
|
||||
.set OFFSET_REG_BG1CNT, 0xa
|
||||
.set OFFSET_REG_BG2CNT, 0xc
|
||||
.set OFFSET_REG_BG3CNT, 0xe
|
||||
.set OFFSET_REG_BG0HOFS, 0x10
|
||||
.set OFFSET_REG_BG0VOFS, 0x12
|
||||
.set OFFSET_REG_BG1HOFS, 0x14
|
||||
.set OFFSET_REG_BG1VOFS, 0x16
|
||||
.set OFFSET_REG_BG2HOFS, 0x18
|
||||
.set OFFSET_REG_BG2VOFS, 0x1a
|
||||
.set OFFSET_REG_BG3HOFS, 0x1c
|
||||
.set OFFSET_REG_BG3VOFS, 0x1e
|
||||
.set OFFSET_REG_BG2PA, 0x20
|
||||
.set OFFSET_REG_BG2PB, 0x22
|
||||
.set OFFSET_REG_BG2PC, 0x24
|
||||
.set OFFSET_REG_BG2PD, 0x26
|
||||
.set OFFSET_REG_BG2X_L, 0x28
|
||||
.set OFFSET_REG_BG2X_H, 0x2a
|
||||
.set OFFSET_REG_BG2Y_L, 0x2c
|
||||
.set OFFSET_REG_BG2Y_H, 0x2e
|
||||
.set OFFSET_REG_BG3PA, 0x30
|
||||
.set OFFSET_REG_BG3PB, 0x32
|
||||
.set OFFSET_REG_BG3PC, 0x34
|
||||
.set OFFSET_REG_BG3PD, 0x36
|
||||
.set OFFSET_REG_BG3X_L, 0x38
|
||||
.set OFFSET_REG_BG3X_H, 0x3a
|
||||
.set OFFSET_REG_BG3Y_L, 0x3c
|
||||
.set OFFSET_REG_BG3Y_H, 0x3e
|
||||
.set OFFSET_REG_WIN0H, 0x40
|
||||
.set OFFSET_REG_WIN1H, 0x42
|
||||
.set OFFSET_REG_WIN0V, 0x44
|
||||
.set OFFSET_REG_WIN1V, 0x46
|
||||
.set OFFSET_REG_WININ, 0x48
|
||||
.set OFFSET_REG_WINOUT, 0x4a
|
||||
.set OFFSET_REG_MOSAIC, 0x4c
|
||||
.set OFFSET_REG_BLDCNT, 0x50
|
||||
.set OFFSET_REG_BLDALPHA, 0x52
|
||||
.set OFFSET_REG_BLDY, 0x54
|
||||
|
||||
.set OFFSET_REG_SOUND1CNT, 0x60
|
||||
.set OFFSET_REG_SOUND1CNT_L, 0x60
|
||||
.set OFFSET_REG_NR10, 0x60
|
||||
.set OFFSET_REG_SOUND1CNT_H, 0x62
|
||||
.set OFFSET_REG_NR11, 0x62
|
||||
.set OFFSET_REG_NR12, 0x63
|
||||
.set OFFSET_REG_SOUND1CNT_X, 0x64
|
||||
.set OFFSET_REG_NR13, 0x64
|
||||
.set OFFSET_REG_NR14, 0x65
|
||||
.set OFFSET_REG_SOUND2CNT, 0x68
|
||||
.set OFFSET_REG_SOUND2CNT_L, 0x68
|
||||
.set OFFSET_REG_NR21, 0x68
|
||||
.set OFFSET_REG_NR22, 0x69
|
||||
.set OFFSET_REG_SOUND2CNT_H, 0x6c
|
||||
.set OFFSET_REG_NR23, 0x6c
|
||||
.set OFFSET_REG_NR24, 0x6d
|
||||
.set OFFSET_REG_SOUND3CNT, 0x70
|
||||
.set OFFSET_REG_SOUND3CNT_L, 0x70
|
||||
.set OFFSET_REG_NR30, 0x70
|
||||
.set OFFSET_REG_SOUND3CNT_H, 0x72
|
||||
.set OFFSET_REG_NR31, 0x72
|
||||
.set OFFSET_REG_NR32, 0x73
|
||||
.set OFFSET_REG_SOUND3CNT_X, 0x74
|
||||
.set OFFSET_REG_NR33, 0x74
|
||||
.set OFFSET_REG_NR34, 0x75
|
||||
.set OFFSET_REG_SOUND4CNT, 0x78
|
||||
.set OFFSET_REG_SOUND4CNT_L, 0x78
|
||||
.set OFFSET_REG_NR41, 0x78
|
||||
.set OFFSET_REG_NR42, 0x79
|
||||
.set OFFSET_REG_SOUND4CNT_H, 0x7c
|
||||
.set OFFSET_REG_NR43, 0x7c
|
||||
.set OFFSET_REG_NR44, 0x7d
|
||||
.set OFFSET_REG_SOUNDCNT, 0x80
|
||||
.set OFFSET_REG_SOUNDCNT_L, 0x80
|
||||
.set OFFSET_REG_NR50, 0x80
|
||||
.set OFFSET_REG_NR51, 0x81
|
||||
.set OFFSET_REG_SOUNDCNT_H, 0x82
|
||||
.set OFFSET_REG_SOUNDCNT_X, 0x84
|
||||
.set OFFSET_REG_NR52, 0x84
|
||||
.set OFFSET_REG_SOUNDBIAS, 0x88
|
||||
.set OFFSET_REG_WAVE_RAM, 0x90
|
||||
.set OFFSET_REG_WAVE_RAM0, 0x90
|
||||
.set OFFSET_REG_WAVE_RAM0_L, 0x90
|
||||
.set OFFSET_REG_WAVE_RAM0_H, 0x92
|
||||
.set OFFSET_REG_WAVE_RAM1, 0x94
|
||||
.set OFFSET_REG_WAVE_RAM1_L, 0x94
|
||||
.set OFFSET_REG_WAVE_RAM1_H, 0x96
|
||||
.set OFFSET_REG_WAVE_RAM2, 0x98
|
||||
.set OFFSET_REG_WAVE_RAM2_L, 0x98
|
||||
.set OFFSET_REG_WAVE_RAM2_H, 0x9a
|
||||
.set OFFSET_REG_WAVE_RAM3, 0x9c
|
||||
.set OFFSET_REG_WAVE_RAM3_L, 0x9c
|
||||
.set OFFSET_REG_WAVE_RAM3_H, 0x9e
|
||||
.set OFFSET_REG_FIFO, 0xa0
|
||||
.set OFFSET_REG_FIFO_A, 0xa0
|
||||
.set OFFSET_REG_FIFO_A_L, 0xa0
|
||||
.set OFFSET_REG_FIFO_A_H, 0xa2
|
||||
.set OFFSET_REG_FIFO_B, 0xa4
|
||||
.set OFFSET_REG_FIFO_B_L, 0xa4
|
||||
.set OFFSET_REG_FIFO_B_H, 0xa6
|
||||
|
||||
.set OFFSET_REG_DMA0, 0xb0
|
||||
.set OFFSET_REG_DMA0SAD, 0xb0
|
||||
.set OFFSET_REG_DMA0SAD_L, 0xb0
|
||||
.set OFFSET_REG_DMA0SAD_H, 0xb2
|
||||
.set OFFSET_REG_DMA0DAD, 0xb4
|
||||
.set OFFSET_REG_DMA0DAD_L, 0xb4
|
||||
.set OFFSET_REG_DMA0DAD_H, 0xb6
|
||||
.set OFFSET_REG_DMA0CNT, 0xb8
|
||||
.set OFFSET_REG_DMA0CNT_L, 0xb8
|
||||
.set OFFSET_REG_DMA0CNT_H, 0xba
|
||||
.set OFFSET_REG_DMA1, 0xbc
|
||||
.set OFFSET_REG_DMA1SAD, 0xbc
|
||||
.set OFFSET_REG_DMA1SAD_L, 0xbc
|
||||
.set OFFSET_REG_DMA1SAD_H, 0xbe
|
||||
.set OFFSET_REG_DMA1DAD, 0xc0
|
||||
.set OFFSET_REG_DMA1DAD_L, 0xc0
|
||||
.set OFFSET_REG_DMA1DAD_H, 0xc2
|
||||
.set OFFSET_REG_DMA1CNT, 0xc4
|
||||
.set OFFSET_REG_DMA1CNT_L, 0xc4
|
||||
.set OFFSET_REG_DMA1CNT_H, 0xc6
|
||||
.set OFFSET_REG_DMA2, 0xc8
|
||||
.set OFFSET_REG_DMA2SAD, 0xc8
|
||||
.set OFFSET_REG_DMA2SAD_L, 0xc8
|
||||
.set OFFSET_REG_DMA2SAD_H, 0xca
|
||||
.set OFFSET_REG_DMA2DAD, 0xcc
|
||||
.set OFFSET_REG_DMA2DAD_L, 0xcc
|
||||
.set OFFSET_REG_DMA2DAD_H, 0xce
|
||||
.set OFFSET_REG_DMA2CNT, 0xd0
|
||||
.set OFFSET_REG_DMA2CNT_L, 0xd0
|
||||
.set OFFSET_REG_DMA2CNT_H, 0xd2
|
||||
.set OFFSET_REG_DMA3, 0xd4
|
||||
.set OFFSET_REG_DMA3SAD, 0xd4
|
||||
.set OFFSET_REG_DMA3SAD_L, 0xd4
|
||||
.set OFFSET_REG_DMA3SAD_H, 0xd6
|
||||
.set OFFSET_REG_DMA3DAD, 0xd8
|
||||
.set OFFSET_REG_DMA3DAD_L, 0xd8
|
||||
.set OFFSET_REG_DMA3DAD_H, 0xda
|
||||
.set OFFSET_REG_DMA3CNT, 0xdc
|
||||
.set OFFSET_REG_DMA3CNT_L, 0xdc
|
||||
.set OFFSET_REG_DMA3CNT_H, 0xde
|
||||
|
||||
.set OFFSET_REG_TM0CNT, 0x100
|
||||
.set OFFSET_REG_TM0CNT_L, 0x100
|
||||
.set OFFSET_REG_TM0CNT_H, 0x102
|
||||
.set OFFSET_REG_TM1CNT, 0x104
|
||||
.set OFFSET_REG_TM1CNT_L, 0x104
|
||||
.set OFFSET_REG_TM1CNT_H, 0x106
|
||||
.set OFFSET_REG_TM2CNT, 0x108
|
||||
.set OFFSET_REG_TM2CNT_L, 0x108
|
||||
.set OFFSET_REG_TM2CNT_H, 0x10a
|
||||
.set OFFSET_REG_TM3CNT, 0x10c
|
||||
.set OFFSET_REG_TM3CNT_L, 0x10c
|
||||
.set OFFSET_REG_TM3CNT_H, 0x10e
|
||||
|
||||
.set OFFSET_REG_SIOCNT, 0x128
|
||||
.set OFFSET_REG_SIODATA8, 0x12a
|
||||
.set OFFSET_REG_SIODATA32, 0x120
|
||||
.set OFFSET_REG_SIOMLT_SEND, 0x12a
|
||||
.set OFFSET_REG_SIOMLT_RECV, 0x120
|
||||
.set OFFSET_REG_SIOMULTI0, 0x120
|
||||
.set OFFSET_REG_SIOMULTI1, 0x122
|
||||
.set OFFSET_REG_SIOMULTI2, 0x124
|
||||
.set OFFSET_REG_SIOMULTI3, 0x126
|
||||
|
||||
.set OFFSET_REG_KEYINPUT, 0x130
|
||||
.set OFFSET_REG_KEYCNT, 0x132
|
||||
|
||||
.set OFFSET_REG_RCNT, 0x134
|
||||
|
||||
.set OFFSET_REG_JOYCNT, 0x140
|
||||
.set OFFSET_REG_JOYSTAT, 0x158
|
||||
.set OFFSET_REG_JOY_RECV, 0x150
|
||||
.set OFFSET_REG_JOY_RECV_L, 0x150
|
||||
.set OFFSET_REG_JOY_RECV_H, 0x152
|
||||
.set OFFSET_REG_JOY_TRANS, 0x154
|
||||
.set OFFSET_REG_JOY_TRANS_L, 0x154
|
||||
.set OFFSET_REG_JOY_TRANS_H, 0x156
|
||||
|
||||
.set OFFSET_REG_IME, 0x208
|
||||
.set OFFSET_REG_IE, 0x200
|
||||
.set OFFSET_REG_IF, 0x202
|
||||
|
||||
.set OFFSET_REG_WAITCNT, 0x204
|
||||
|
||||
@ I/O register addresses
|
||||
.set REG_DISPCNT, REG_BASE + OFFSET_REG_DISPCNT
|
||||
.set REG_DISPSTAT, REG_BASE + OFFSET_REG_DISPSTAT
|
||||
.set REG_VCOUNT, REG_BASE + OFFSET_REG_VCOUNT
|
||||
.set REG_BG0CNT, REG_BASE + OFFSET_REG_BG0CNT
|
||||
.set REG_BG1CNT, REG_BASE + OFFSET_REG_BG1CNT
|
||||
.set REG_BG2CNT, REG_BASE + OFFSET_REG_BG2CNT
|
||||
.set REG_BG3CNT, REG_BASE + OFFSET_REG_BG3CNT
|
||||
.set REG_BG0HOFS, REG_BASE + OFFSET_REG_BG0HOFS
|
||||
.set REG_BG0VOFS, REG_BASE + OFFSET_REG_BG0VOFS
|
||||
.set REG_BG1HOFS, REG_BASE + OFFSET_REG_BG1HOFS
|
||||
.set REG_BG1VOFS, REG_BASE + OFFSET_REG_BG1VOFS
|
||||
.set REG_BG2HOFS, REG_BASE + OFFSET_REG_BG2HOFS
|
||||
.set REG_BG2VOFS, REG_BASE + OFFSET_REG_BG2VOFS
|
||||
.set REG_BG3HOFS, REG_BASE + OFFSET_REG_BG3HOFS
|
||||
.set REG_BG3VOFS, REG_BASE + OFFSET_REG_BG3VOFS
|
||||
.set REG_BG2PA, REG_BASE + OFFSET_REG_BG2PA
|
||||
.set REG_BG2PB, REG_BASE + OFFSET_REG_BG2PB
|
||||
.set REG_BG2PC, REG_BASE + OFFSET_REG_BG2PC
|
||||
.set REG_BG2PD, REG_BASE + OFFSET_REG_BG2PD
|
||||
.set REG_BG2X_L, REG_BASE + OFFSET_REG_BG2X_L
|
||||
.set REG_BG2X_H, REG_BASE + OFFSET_REG_BG2X_H
|
||||
.set REG_BG2Y_L, REG_BASE + OFFSET_REG_BG2Y_L
|
||||
.set REG_BG2Y_H, REG_BASE + OFFSET_REG_BG2Y_H
|
||||
.set REG_BG3PA, REG_BASE + OFFSET_REG_BG3PA
|
||||
.set REG_BG3PB, REG_BASE + OFFSET_REG_BG3PB
|
||||
.set REG_BG3PC, REG_BASE + OFFSET_REG_BG3PC
|
||||
.set REG_BG3PD, REG_BASE + OFFSET_REG_BG3PD
|
||||
.set REG_BG3X_L, REG_BASE + OFFSET_REG_BG3X_L
|
||||
.set REG_BG3X_H, REG_BASE + OFFSET_REG_BG3X_H
|
||||
.set REG_BG3Y_L, REG_BASE + OFFSET_REG_BG3Y_L
|
||||
.set REG_BG3Y_H, REG_BASE + OFFSET_REG_BG3Y_H
|
||||
.set REG_WIN0H, REG_BASE + OFFSET_REG_WIN0H
|
||||
.set REG_WIN1H, REG_BASE + OFFSET_REG_WIN1H
|
||||
.set REG_WIN0V, REG_BASE + OFFSET_REG_WIN0V
|
||||
.set REG_WIN1V, REG_BASE + OFFSET_REG_WIN1V
|
||||
.set REG_WININ, REG_BASE + OFFSET_REG_WININ
|
||||
.set REG_WINOUT, REG_BASE + OFFSET_REG_WINOUT
|
||||
.set REG_MOSAIC, REG_BASE + OFFSET_REG_MOSAIC
|
||||
.set REG_BLDCNT, REG_BASE + OFFSET_REG_BLDCNT
|
||||
.set REG_BLDALPHA, REG_BASE + OFFSET_REG_BLDALPHA
|
||||
.set REG_BLDY, REG_BASE + OFFSET_REG_BLDY
|
||||
|
||||
.set REG_SOUND1CNT, REG_BASE + OFFSET_REG_SOUND1CNT
|
||||
.set REG_SOUND1CNT_L, REG_BASE + OFFSET_REG_SOUND1CNT_L
|
||||
.set REG_NR10, REG_BASE + OFFSET_REG_NR10
|
||||
.set REG_SOUND1CNT_H, REG_BASE + OFFSET_REG_SOUND1CNT_H
|
||||
.set REG_NR11, REG_BASE + OFFSET_REG_NR11
|
||||
.set REG_NR12, REG_BASE + OFFSET_REG_NR12
|
||||
.set REG_SOUND1CNT_X, REG_BASE + OFFSET_REG_SOUND1CNT_X
|
||||
.set REG_NR13, REG_BASE + OFFSET_REG_NR13
|
||||
.set REG_NR14, REG_BASE + OFFSET_REG_NR14
|
||||
.set REG_SOUND2CNT, REG_BASE + OFFSET_REG_SOUND2CNT
|
||||
.set REG_SOUND2CNT_L, REG_BASE + OFFSET_REG_SOUND2CNT_L
|
||||
.set REG_NR21, REG_BASE + OFFSET_REG_NR21
|
||||
.set REG_NR22, REG_BASE + OFFSET_REG_NR22
|
||||
.set REG_SOUND2CNT_H, REG_BASE + OFFSET_REG_SOUND2CNT_H
|
||||
.set REG_NR23, REG_BASE + OFFSET_REG_NR23
|
||||
.set REG_NR24, REG_BASE + OFFSET_REG_NR24
|
||||
.set REG_SOUND3CNT, REG_BASE + OFFSET_REG_SOUND3CNT
|
||||
.set REG_SOUND3CNT_L, REG_BASE + OFFSET_REG_SOUND3CNT_L
|
||||
.set REG_NR30, REG_BASE + OFFSET_REG_NR30
|
||||
.set REG_SOUND3CNT_H, REG_BASE + OFFSET_REG_SOUND3CNT_H
|
||||
.set REG_NR31, REG_BASE + OFFSET_REG_NR31
|
||||
.set REG_NR32, REG_BASE + OFFSET_REG_NR32
|
||||
.set REG_SOUND3CNT_X, REG_BASE + OFFSET_REG_SOUND3CNT_X
|
||||
.set REG_NR33, REG_BASE + OFFSET_REG_NR33
|
||||
.set REG_NR34, REG_BASE + OFFSET_REG_NR34
|
||||
.set REG_SOUND4CNT, REG_BASE + OFFSET_REG_SOUND4CNT
|
||||
.set REG_SOUND4CNT_L, REG_BASE + OFFSET_REG_SOUND4CNT_L
|
||||
.set REG_NR41, REG_BASE + OFFSET_REG_NR41
|
||||
.set REG_NR42, REG_BASE + OFFSET_REG_NR42
|
||||
.set REG_SOUND4CNT_H, REG_BASE + OFFSET_REG_SOUND4CNT_H
|
||||
.set REG_NR43, REG_BASE + OFFSET_REG_NR43
|
||||
.set REG_NR44, REG_BASE + OFFSET_REG_NR44
|
||||
.set REG_SOUNDCNT, REG_BASE + OFFSET_REG_SOUNDCNT
|
||||
.set REG_SOUNDCNT_L, REG_BASE + OFFSET_REG_SOUNDCNT_L
|
||||
.set REG_NR50, REG_BASE + OFFSET_REG_NR50
|
||||
.set REG_NR51, REG_BASE + OFFSET_REG_NR51
|
||||
.set REG_SOUNDCNT_H, REG_BASE + OFFSET_REG_SOUNDCNT_H
|
||||
.set REG_SOUNDCNT_X, REG_BASE + OFFSET_REG_SOUNDCNT_X
|
||||
.set REG_NR52, REG_BASE + OFFSET_REG_NR52
|
||||
.set REG_SOUNDBIAS, REG_BASE + OFFSET_REG_SOUNDBIAS
|
||||
.set REG_WAVE_RAM, REG_BASE + OFFSET_REG_WAVE_RAM
|
||||
.set REG_WAVE_RAM0, REG_BASE + OFFSET_REG_WAVE_RAM0
|
||||
.set REG_WAVE_RAM0_L, REG_BASE + OFFSET_REG_WAVE_RAM0_L
|
||||
.set REG_WAVE_RAM0_H, REG_BASE + OFFSET_REG_WAVE_RAM0_H
|
||||
.set REG_WAVE_RAM1, REG_BASE + OFFSET_REG_WAVE_RAM1
|
||||
.set REG_WAVE_RAM1_L, REG_BASE + OFFSET_REG_WAVE_RAM1_L
|
||||
.set REG_WAVE_RAM1_H, REG_BASE + OFFSET_REG_WAVE_RAM1_H
|
||||
.set REG_WAVE_RAM2, REG_BASE + OFFSET_REG_WAVE_RAM2
|
||||
.set REG_WAVE_RAM2_L, REG_BASE + OFFSET_REG_WAVE_RAM2_L
|
||||
.set REG_WAVE_RAM2_H, REG_BASE + OFFSET_REG_WAVE_RAM2_H
|
||||
.set REG_WAVE_RAM3, REG_BASE + OFFSET_REG_WAVE_RAM3
|
||||
.set REG_WAVE_RAM3_L, REG_BASE + OFFSET_REG_WAVE_RAM3_L
|
||||
.set REG_WAVE_RAM3_H, REG_BASE + OFFSET_REG_WAVE_RAM3_H
|
||||
.set REG_FIFO, REG_BASE + OFFSET_REG_FIFO
|
||||
.set REG_FIFO_A, REG_BASE + OFFSET_REG_FIFO_A
|
||||
.set REG_FIFO_A_L, REG_BASE + OFFSET_REG_FIFO_A_L
|
||||
.set REG_FIFO_A_H, REG_BASE + OFFSET_REG_FIFO_A_H
|
||||
.set REG_FIFO_B, REG_BASE + OFFSET_REG_FIFO_B
|
||||
.set REG_FIFO_B_L, REG_BASE + OFFSET_REG_FIFO_B_L
|
||||
.set REG_FIFO_B_H, REG_BASE + OFFSET_REG_FIFO_B_H
|
||||
|
||||
.set REG_DMA0, REG_BASE + OFFSET_REG_DMA0
|
||||
.set REG_DMA0SAD, REG_BASE + OFFSET_REG_DMA0SAD
|
||||
.set REG_DMA0SAD_L, REG_BASE + OFFSET_REG_DMA0SAD_L
|
||||
.set REG_DMA0SAD_H, REG_BASE + OFFSET_REG_DMA0SAD_H
|
||||
.set REG_DMA0DAD, REG_BASE + OFFSET_REG_DMA0DAD
|
||||
.set REG_DMA0DAD_L, REG_BASE + OFFSET_REG_DMA0DAD_L
|
||||
.set REG_DMA0DAD_H, REG_BASE + OFFSET_REG_DMA0DAD_H
|
||||
.set REG_DMA0CNT, REG_BASE + OFFSET_REG_DMA0CNT
|
||||
.set REG_DMA0CNT_L, REG_BASE + OFFSET_REG_DMA0CNT_L
|
||||
.set REG_DMA0CNT_H, REG_BASE + OFFSET_REG_DMA0CNT_H
|
||||
.set REG_DMA1, REG_BASE + OFFSET_REG_DMA1
|
||||
.set REG_DMA1SAD, REG_BASE + OFFSET_REG_DMA1SAD
|
||||
.set REG_DMA1SAD_L, REG_BASE + OFFSET_REG_DMA1SAD_L
|
||||
.set REG_DMA1SAD_H, REG_BASE + OFFSET_REG_DMA1SAD_H
|
||||
.set REG_DMA1DAD, REG_BASE + OFFSET_REG_DMA1DAD
|
||||
.set REG_DMA1DAD_L, REG_BASE + OFFSET_REG_DMA1DAD_L
|
||||
.set REG_DMA1DAD_H, REG_BASE + OFFSET_REG_DMA1DAD_H
|
||||
.set REG_DMA1CNT, REG_BASE + OFFSET_REG_DMA1CNT
|
||||
.set REG_DMA1CNT_L, REG_BASE + OFFSET_REG_DMA1CNT_L
|
||||
.set REG_DMA1CNT_H, REG_BASE + OFFSET_REG_DMA1CNT_H
|
||||
.set REG_DMA2, REG_BASE + OFFSET_REG_DMA2
|
||||
.set REG_DMA2SAD, REG_BASE + OFFSET_REG_DMA2SAD
|
||||
.set REG_DMA2SAD_L, REG_BASE + OFFSET_REG_DMA2SAD_L
|
||||
.set REG_DMA2SAD_H, REG_BASE + OFFSET_REG_DMA2SAD_H
|
||||
.set REG_DMA2DAD, REG_BASE + OFFSET_REG_DMA2DAD
|
||||
.set REG_DMA2DAD_L, REG_BASE + OFFSET_REG_DMA2DAD_L
|
||||
.set REG_DMA2DAD_H, REG_BASE + OFFSET_REG_DMA2DAD_H
|
||||
.set REG_DMA2CNT, REG_BASE + OFFSET_REG_DMA2CNT
|
||||
.set REG_DMA2CNT_L, REG_BASE + OFFSET_REG_DMA2CNT_L
|
||||
.set REG_DMA2CNT_H, REG_BASE + OFFSET_REG_DMA2CNT_H
|
||||
.set REG_DMA3, REG_BASE + OFFSET_REG_DMA3
|
||||
.set REG_DMA3SAD, REG_BASE + OFFSET_REG_DMA3SAD
|
||||
.set REG_DMA3SAD_L, REG_BASE + OFFSET_REG_DMA3SAD_L
|
||||
.set REG_DMA3SAD_H, REG_BASE + OFFSET_REG_DMA3SAD_H
|
||||
.set REG_DMA3DAD, REG_BASE + OFFSET_REG_DMA3DAD
|
||||
.set REG_DMA3DAD_L, REG_BASE + OFFSET_REG_DMA3DAD_L
|
||||
.set REG_DMA3DAD_H, REG_BASE + OFFSET_REG_DMA3DAD_H
|
||||
.set REG_DMA3CNT, REG_BASE + OFFSET_REG_DMA3CNT
|
||||
.set REG_DMA3CNT_L, REG_BASE + OFFSET_REG_DMA3CNT_L
|
||||
.set REG_DMA3CNT_H, REG_BASE + OFFSET_REG_DMA3CNT_H
|
||||
|
||||
.set REG_TM0CNT, REG_BASE + OFFSET_REG_TM0CNT
|
||||
.set REG_TM0CNT_L, REG_BASE + OFFSET_REG_TM0CNT_L
|
||||
.set REG_TM0CNT_H, REG_BASE + OFFSET_REG_TM0CNT_H
|
||||
.set REG_TM1CNT, REG_BASE + OFFSET_REG_TM1CNT
|
||||
.set REG_TM1CNT_L, REG_BASE + OFFSET_REG_TM1CNT_L
|
||||
.set REG_TM1CNT_H, REG_BASE + OFFSET_REG_TM1CNT_H
|
||||
.set REG_TM2CNT, REG_BASE + OFFSET_REG_TM2CNT
|
||||
.set REG_TM2CNT_L, REG_BASE + OFFSET_REG_TM2CNT_L
|
||||
.set REG_TM2CNT_H, REG_BASE + OFFSET_REG_TM2CNT_H
|
||||
.set REG_TM3CNT, REG_BASE + OFFSET_REG_TM3CNT
|
||||
.set REG_TM3CNT_L, REG_BASE + OFFSET_REG_TM3CNT_L
|
||||
.set REG_TM3CNT_H, REG_BASE + OFFSET_REG_TM3CNT_H
|
||||
|
||||
.set REG_SIOCNT, REG_BASE + OFFSET_REG_SIOCNT
|
||||
.set REG_SIODATA8, REG_BASE + OFFSET_REG_SIODATA8
|
||||
.set REG_SIODATA32, REG_BASE + OFFSET_REG_SIODATA32
|
||||
.set REG_SIOMLT_SEND, REG_BASE + OFFSET_REG_SIOMLT_SEND
|
||||
.set REG_SIOMLT_RECV, REG_BASE + OFFSET_REG_SIOMLT_RECV
|
||||
.set REG_SIOMULTI0, REG_BASE + OFFSET_REG_SIOMULTI0
|
||||
.set REG_SIOMULTI1, REG_BASE + OFFSET_REG_SIOMULTI1
|
||||
.set REG_SIOMULTI2, REG_BASE + OFFSET_REG_SIOMULTI2
|
||||
.set REG_SIOMULTI3, REG_BASE + OFFSET_REG_SIOMULTI3
|
||||
|
||||
.set REG_KEYINPUT, REG_BASE + OFFSET_REG_KEYINPUT
|
||||
.set REG_KEYCNT, REG_BASE + OFFSET_REG_KEYCNT
|
||||
|
||||
.set REG_RCNT, REG_BASE + OFFSET_REG_RCNT
|
||||
|
||||
.set REG_JOYCNT, REG_BASE + OFFSET_REG_JOYCNT
|
||||
.set REG_JOYSTAT, REG_BASE + OFFSET_REG_JOYSTAT
|
||||
.set REG_JOY_RECV, REG_BASE + OFFSET_REG_JOY_RECV
|
||||
.set REG_JOY_RECV_L, REG_BASE + OFFSET_REG_JOY_RECV_L
|
||||
.set REG_JOY_RECV_H, REG_BASE + OFFSET_REG_JOY_RECV_H
|
||||
.set REG_JOY_TRANS, REG_BASE + OFFSET_REG_JOY_TRANS
|
||||
.set REG_JOY_TRANS_L, REG_BASE + OFFSET_REG_JOY_TRANS_L
|
||||
.set REG_JOY_TRANS_H, REG_BASE + OFFSET_REG_JOY_TRANS_H
|
||||
|
||||
.set REG_IME, REG_BASE + OFFSET_REG_IME
|
||||
.set REG_IE, REG_BASE + OFFSET_REG_IE
|
||||
.set REG_IF, REG_BASE + OFFSET_REG_IF
|
||||
|
||||
.set REG_WAITCNT, REG_BASE + OFFSET_REG_WAITCNT
|
||||
|
||||
@ DMA register constants
|
||||
|
||||
.set DMA_DEST_INC, 0x0000
|
||||
.set DMA_DEST_DEC, 0x0020
|
||||
.set DMA_DEST_FIXED, 0x0040
|
||||
.set DMA_DEST_RELOAD, 0x0060
|
||||
.set DMA_SRC_INC, 0x0000
|
||||
.set DMA_SRC_DEC, 0x0080
|
||||
.set DMA_SRC_FIXED, 0x0100
|
||||
.set DMA_REPEAT, 0x0200
|
||||
.set DMA_16BIT, 0x0000
|
||||
.set DMA_32BIT, 0x0400
|
||||
.set DMA_DREQ_ON, 0x0800
|
||||
.set DMA_START_NOW, 0x0000
|
||||
.set DMA_START_VBLANK, 0x1000
|
||||
.set DMA_START_HBLANK, 0x2000
|
||||
.set DMA_START_SPECIAL, 0x3000
|
||||
.set DMA_INTR_ENABLE, 0x4000
|
||||
.set DMA_ENABLE, 0x8000
|
||||
|
||||
@ OAM attribute constants
|
||||
|
||||
.set OAM_OBJ_NORMAL, 0x00000000
|
||||
.set OAM_OBJ_BLEND, 0x00000400
|
||||
.set OAM_OBJ_WINDOW, 0x00000800
|
||||
|
||||
.set OAM_AFFINE_NONE, 0x00000000
|
||||
.set OAM_AFFINE_NORMAL_SIZE, 0x00000100
|
||||
.set OAM_OBJ_DISABLED, 0x00000200
|
||||
.set OAM_AFFINE_DOUBLE_SIZE, 0x00000300
|
||||
|
||||
.set OAM_MOSAIC_OFF, 0x00000000
|
||||
.set OAM_MOSAIC_ON, 0x00001000
|
||||
|
||||
.set OAM_4BPP, 0x00000000
|
||||
.set OAM_8BPP, 0x00002000
|
||||
|
||||
.set OAM_H_FLIP, 0x10000000
|
||||
.set OAM_V_FLIP, 0x20000000
|
||||
|
||||
.set OAM_SQUARE, 0x00000000
|
||||
.set OAM_H_RECTANGLE, 0x00004000
|
||||
.set OAM_V_RECTANGLE, 0x00008000
|
||||
.set OAM_SIZE_0, 0x00000000
|
||||
.set OAM_SIZE_1, 0x40000000
|
||||
.set OAM_SIZE_2, 0x80000000
|
||||
.set OAM_SIZE_3, 0xc0000000
|
||||
|
||||
.set OAM_SIZE_8x8, OAM_SIZE_0 | OAM_SQUARE
|
||||
.set OAM_SIZE_16x16, OAM_SIZE_1 | OAM_SQUARE
|
||||
.set OAM_SIZE_32x32, OAM_SIZE_2 | OAM_SQUARE
|
||||
.set OAM_SIZE_64x64, OAM_SIZE_3 | OAM_SQUARE
|
||||
|
||||
.set OAM_SIZE_16x8, OAM_SIZE_0 | OAM_H_RECTANGLE
|
||||
.set OAM_SIZE_32x8, OAM_SIZE_1 | OAM_H_RECTANGLE
|
||||
.set OAM_SIZE_32x16, OAM_SIZE_2 | OAM_H_RECTANGLE
|
||||
.set OAM_SIZE_64x32, OAM_SIZE_3 | OAM_H_RECTANGLE
|
||||
|
||||
.set OAM_SIZE_8x16, OAM_SIZE_0 | OAM_V_RECTANGLE
|
||||
.set OAM_SIZE_8x32, OAM_SIZE_1 | OAM_V_RECTANGLE
|
||||
.set OAM_SIZE_16x32, OAM_SIZE_2 | OAM_V_RECTANGLE
|
||||
.set OAM_SIZE_32x64, OAM_SIZE_3 | OAM_V_RECTANGLE
|
||||
@@ -1,7 +1,7 @@
|
||||
#ifndef GUARD_FLASH_H
|
||||
#define GUARD_FLASH_H
|
||||
|
||||
#include <gba/gba.h>
|
||||
#include "gba/gba.h"
|
||||
|
||||
enum
|
||||
{
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
#ifndef GUARD_GBA_DEFINES
|
||||
#define GUARD_GBA_DEFINES
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
#define BSS_DATA __attribute__((section(".bss")))
|
||||
#define IWRAM_DATA __attribute__((section("iwram_data")))
|
||||
#define EWRAM_DATA __attribute__((section("ewram_data")))
|
||||
#define UNUSED __attribute__((unused))
|
||||
#define NAKED __attribute__((naked))
|
||||
|
||||
#define ALIGNED(n) __attribute__((aligned(n)))
|
||||
|
||||
#define SOUND_INFO_PTR (*(struct SoundInfo **)0x3007FF0)
|
||||
#define INTR_CHECK (*(u16 *)0x3007FF8)
|
||||
#define INTR_VECTOR (*(void **)0x3007FFC)
|
||||
|
||||
#define EWRAM_START 0x02000000
|
||||
#define EWRAM_END (EWRAM_START + 0x40000)
|
||||
#define IWRAM_START 0x03000000
|
||||
#define IWRAM_END (IWRAM_START + 0x8000)
|
||||
|
||||
#define PLTT 0x5000000
|
||||
#define PLTT_SIZE 0x400
|
||||
|
||||
#define BG_PLTT PLTT
|
||||
#define BG_PLTT_SIZE 0x200
|
||||
|
||||
#define OBJ_PLTT (PLTT + 0x200)
|
||||
#define OBJ_PLTT_SIZE 0x200
|
||||
|
||||
#define VRAM 0x6000000
|
||||
#define VRAM_SIZE 0x18000
|
||||
|
||||
#define BG_VRAM VRAM
|
||||
#define BG_VRAM_SIZE 0x10000
|
||||
#define BG_CHAR_SIZE 0x4000
|
||||
#define BG_SCREEN_SIZE 0x800
|
||||
#define BG_CHAR_ADDR(n) (void *)(BG_VRAM + (0x4000 * (n)))
|
||||
#define BG_SCREEN_ADDR(n) (void *)(BG_VRAM + (0x800 * (n)))
|
||||
#define BG_TILE_ADDR(n) (void *)(BG_VRAM + (0x80 * (n)))
|
||||
|
||||
#define BG_TILE_H_FLIP(n) (0x400 + (n))
|
||||
#define BG_TILE_V_FLIP(n) (0x800 + (n))
|
||||
|
||||
// text-mode BG
|
||||
#define OBJ_VRAM0 (void *)(VRAM + 0x10000)
|
||||
#define OBJ_VRAM0_SIZE 0x8000
|
||||
|
||||
// bitmap-mode BG
|
||||
#define OBJ_VRAM1 (void *)(VRAM + 0x14000)
|
||||
#define OBJ_VRAM1_SIZE 0x4000
|
||||
|
||||
#define OAM 0x7000000
|
||||
#define OAM_SIZE 0x400
|
||||
|
||||
#define ROM_HEADER_SIZE 0xC0
|
||||
|
||||
#define DISPLAY_WIDTH 240
|
||||
#define DISPLAY_HEIGHT 160
|
||||
|
||||
#define TILE_SIZE_4BPP 32
|
||||
#define TILE_SIZE_8BPP 64
|
||||
|
||||
#define TILE_OFFSET_4BPP(n) ((n) * TILE_SIZE_4BPP)
|
||||
#define TILE_OFFSET_8BPP(n) ((n) * TILE_SIZE_8BPP)
|
||||
|
||||
#define TOTAL_OBJ_TILE_COUNT 1024
|
||||
|
||||
#define RGB(r, g, b) ((r) | ((g) << 5) | ((b) << 10))
|
||||
#define RGB2(r, g, b) (((b) << 10) | ((g) << 5) | (r))
|
||||
#define _RGB(r, g, b) ((((b) & 0x1F) << 10) + (((g) & 0x1F) << 5) + ((r) & 0x1F))
|
||||
|
||||
#define RGB_BLACK RGB(0, 0, 0)
|
||||
#define RGB_WHITE RGB(31, 31, 31)
|
||||
#define RGB_RED RGB(31, 0, 0)
|
||||
#define RGB_GREEN RGB(0, 31, 0)
|
||||
#define RGB_BLUE RGB(0, 0, 31)
|
||||
#define RGB_YELLOW RGB(31, 31, 0)
|
||||
#define RGB_MAGENTA RGB(31, 0, 31)
|
||||
#define RGB_CYAN RGB(0, 31, 31)
|
||||
#define RGB_WHITEALPHA (RGB_WHITE | 0x8000)
|
||||
|
||||
#endif // GUARD_GBA_DEFINES
|
||||
@@ -0,0 +1,85 @@
|
||||
#ifndef GUARD_GBA_FLASH_INTERNAL_H
|
||||
#define GUARD_GBA_FLASH_INTERNAL_H
|
||||
|
||||
#include "gba/gba.h"
|
||||
|
||||
#define FLASH_BASE ((u8 *)0xE000000)
|
||||
|
||||
#define FLASH_WRITE(addr, data) ((*(vu8 *)(FLASH_BASE + (addr))) = (data))
|
||||
|
||||
#define FLASH_ROM_SIZE_1M 131072 // 1 megabit ROM
|
||||
|
||||
#define SECTORS_PER_BANK 16
|
||||
|
||||
struct FlashSector
|
||||
{
|
||||
u32 size;
|
||||
u8 shift;
|
||||
u16 count;
|
||||
u16 top;
|
||||
};
|
||||
|
||||
struct FlashType {
|
||||
u32 romSize;
|
||||
struct FlashSector sector;
|
||||
u16 wait[2]; // game pak bus read/write wait
|
||||
|
||||
// TODO: add support for anonymous unions/structs if possible
|
||||
union {
|
||||
struct {
|
||||
u8 makerId;
|
||||
u8 deviceId;
|
||||
} separate;
|
||||
u16 joined;
|
||||
} ids;
|
||||
};
|
||||
|
||||
struct FlashSetupInfo
|
||||
{
|
||||
u16 (*programFlashByte)(u16, u32, u8);
|
||||
u16 (*programFlashSector)(u16, void *);
|
||||
u16 (*eraseFlashChip)(void);
|
||||
u16 (*eraseFlashSector)(u16);
|
||||
u16 (*WaitForFlashWrite)(u8, u8 *, u8);
|
||||
const u16 *maxTime;
|
||||
struct FlashType type;
|
||||
};
|
||||
|
||||
extern u16 gFlashNumRemainingBytes;
|
||||
|
||||
extern u16 (*ProgramFlashByte)(u16, u32, u8);
|
||||
extern u16 (*ProgramFlashSector)(u16, void *);
|
||||
extern u16 (*EraseFlashChip)(void);
|
||||
extern u16 (*EraseFlashSector)(u16);
|
||||
extern u16 (*WaitForFlashWrite)(u8, u8 *, u8);
|
||||
extern const u16 *gFlashMaxTime;
|
||||
extern const struct FlashType *gFlash;
|
||||
|
||||
extern u8 (*PollFlashStatus)(u8 *);
|
||||
extern u8 gFlashTimeoutFlag;
|
||||
|
||||
extern const struct FlashSetupInfo MX29L010;
|
||||
extern const struct FlashSetupInfo LE26FV10N1TS;
|
||||
extern const struct FlashSetupInfo DefaultFlash;
|
||||
|
||||
void SwitchFlashBank(u8 bankNum);
|
||||
u16 ReadFlashId(void);
|
||||
void StartFlashTimer(u8 phase);
|
||||
void SetReadFlash1(u16 *dest);
|
||||
void StopFlashTimer(void);
|
||||
u16 SetFlashTimerIntr(u8 timerNum, void (**intrFunc)(void));
|
||||
u32 ProgramFlashSectorAndVerify(u16 sectorNum, u8 *src);
|
||||
void ReadFlash(u16 sectorNum, u32 offset, void *dest, u32 size);
|
||||
u32 ProgramFlashSectorAndVerifyNBytes(u16 sectorNum, void *dataSrc, u32 n);
|
||||
|
||||
u16 WaitForFlashWrite_Common(u8 phase, u8 *addr, u8 lastData);
|
||||
|
||||
u16 EraseFlashChip_MX(void);
|
||||
u16 EraseFlashSector_MX(u16 sectorNum);
|
||||
u16 ProgramFlashByte_MX(u16 sectorNum, u32 offset, u8 data);
|
||||
u16 ProgramFlashSector_MX(u16 sectorNum, void *src);
|
||||
|
||||
// agb_flash_1m
|
||||
u32 IdentifyFlash(void);
|
||||
|
||||
#endif // GUARD_GBA_FLASH_INTERNAL_H
|
||||
@@ -0,0 +1,12 @@
|
||||
#ifndef GUARD_GBA_GBA_H
|
||||
#define GUARD_GBA_GBA_H
|
||||
|
||||
#include "gba/defines.h"
|
||||
#include "gba/io_reg.h"
|
||||
#include "gba/types.h"
|
||||
#include "gba/multiboot.h"
|
||||
#include "gba/syscall.h"
|
||||
#include "gba/macro.h"
|
||||
#include "gba/isagbprint.h"
|
||||
|
||||
#endif // GUARD_GBA_GBA_H
|
||||
@@ -0,0 +1,770 @@
|
||||
#ifndef GUARD_GBA_IO_REG_H
|
||||
#define GUARD_GBA_IO_REG_H
|
||||
|
||||
#define REG_BASE 0x4000000 // I/O register base address
|
||||
|
||||
// I/O register offsets
|
||||
|
||||
#define REG_OFFSET_DISPCNT 0x0
|
||||
#define REG_OFFSET_DISPSTAT 0x4
|
||||
#define REG_OFFSET_VCOUNT 0x6
|
||||
#define REG_OFFSET_BG0CNT 0x8
|
||||
#define REG_OFFSET_BG1CNT 0xa
|
||||
#define REG_OFFSET_BG2CNT 0xc
|
||||
#define REG_OFFSET_BG3CNT 0xe
|
||||
#define REG_OFFSET_BG0HOFS 0x10
|
||||
#define REG_OFFSET_BG0VOFS 0x12
|
||||
#define REG_OFFSET_BG1HOFS 0x14
|
||||
#define REG_OFFSET_BG1VOFS 0x16
|
||||
#define REG_OFFSET_BG2HOFS 0x18
|
||||
#define REG_OFFSET_BG2VOFS 0x1a
|
||||
#define REG_OFFSET_BG3HOFS 0x1c
|
||||
#define REG_OFFSET_BG3VOFS 0x1e
|
||||
#define REG_OFFSET_BG2PA 0x20
|
||||
#define REG_OFFSET_BG2PB 0x22
|
||||
#define REG_OFFSET_BG2PC 0x24
|
||||
#define REG_OFFSET_BG2PD 0x26
|
||||
#define REG_OFFSET_BG2X 0x28
|
||||
#define REG_OFFSET_BG2X_L 0x28
|
||||
#define REG_OFFSET_BG2X_H 0x2a
|
||||
#define REG_OFFSET_BG2Y 0x2c
|
||||
#define REG_OFFSET_BG2Y_L 0x2c
|
||||
#define REG_OFFSET_BG2Y_H 0x2e
|
||||
#define REG_OFFSET_BG3PA 0x30
|
||||
#define REG_OFFSET_BG3PB 0x32
|
||||
#define REG_OFFSET_BG3PC 0x34
|
||||
#define REG_OFFSET_BG3PD 0x36
|
||||
#define REG_OFFSET_BG3X 0x38
|
||||
#define REG_OFFSET_BG3X_L 0x38
|
||||
#define REG_OFFSET_BG3X_H 0x3a
|
||||
#define REG_OFFSET_BG3Y 0x3c
|
||||
#define REG_OFFSET_BG3Y_L 0x3c
|
||||
#define REG_OFFSET_BG3Y_H 0x3e
|
||||
#define REG_OFFSET_WIN0H 0x40
|
||||
#define REG_OFFSET_WIN1H 0x42
|
||||
#define REG_OFFSET_WIN0V 0x44
|
||||
#define REG_OFFSET_WIN1V 0x46
|
||||
#define REG_OFFSET_WININ 0x48
|
||||
#define REG_OFFSET_WINOUT 0x4a
|
||||
#define REG_OFFSET_MOSAIC 0x4c
|
||||
#define REG_OFFSET_BLDCNT 0x50
|
||||
#define REG_OFFSET_BLDALPHA 0x52
|
||||
#define REG_OFFSET_BLDY 0x54
|
||||
|
||||
#define REG_OFFSET_SOUND1CNT_L 0x60
|
||||
#define REG_OFFSET_NR10 0x60
|
||||
#define REG_OFFSET_SOUND1CNT_H 0x62
|
||||
#define REG_OFFSET_NR11 0x62
|
||||
#define REG_OFFSET_NR12 0x63
|
||||
#define REG_OFFSET_SOUND1CNT_X 0x64
|
||||
#define REG_OFFSET_NR13 0x64
|
||||
#define REG_OFFSET_NR14 0x65
|
||||
#define REG_OFFSET_SOUND2CNT_L 0x68
|
||||
#define REG_OFFSET_NR21 0x68
|
||||
#define REG_OFFSET_NR22 0x69
|
||||
#define REG_OFFSET_SOUND2CNT_H 0x6c
|
||||
#define REG_OFFSET_NR23 0x6c
|
||||
#define REG_OFFSET_NR24 0x6d
|
||||
#define REG_OFFSET_SOUND3CNT_L 0x70
|
||||
#define REG_OFFSET_NR30 0x70
|
||||
#define REG_OFFSET_SOUND3CNT_H 0x72
|
||||
#define REG_OFFSET_NR31 0x72
|
||||
#define REG_OFFSET_NR32 0x73
|
||||
#define REG_OFFSET_SOUND3CNT_X 0x74
|
||||
#define REG_OFFSET_NR33 0x74
|
||||
#define REG_OFFSET_NR34 0x75
|
||||
#define REG_OFFSET_SOUND4CNT_L 0x78
|
||||
#define REG_OFFSET_NR41 0x78
|
||||
#define REG_OFFSET_NR42 0x79
|
||||
#define REG_OFFSET_SOUND4CNT_H 0x7c
|
||||
#define REG_OFFSET_NR43 0x7c
|
||||
#define REG_OFFSET_NR44 0x7d
|
||||
#define REG_OFFSET_SOUNDCNT_L 0x80
|
||||
#define REG_OFFSET_NR50 0x80
|
||||
#define REG_OFFSET_NR51 0x81
|
||||
#define REG_OFFSET_SOUNDCNT_H 0x82
|
||||
#define REG_OFFSET_SOUNDCNT_X 0x84
|
||||
#define REG_OFFSET_NR52 0x84
|
||||
#define REG_OFFSET_SOUNDBIAS 0x88
|
||||
#define REG_OFFSET_SOUNDBIAS_L 0x88
|
||||
#define REG_OFFSET_SOUNDBIAS_H 0x89
|
||||
#define REG_OFFSET_WAVE_RAM0 0x90
|
||||
#define REG_OFFSET_WAVE_RAM1 0x94
|
||||
#define REG_OFFSET_WAVE_RAM2 0x98
|
||||
#define REG_OFFSET_WAVE_RAM3 0x9c
|
||||
#define REG_OFFSET_FIFO_A 0xa0
|
||||
#define REG_OFFSET_FIFO_B 0xa4
|
||||
|
||||
#define REG_OFFSET_DMA0 0xb0
|
||||
#define REG_OFFSET_DMA0SAD 0xb0
|
||||
#define REG_OFFSET_DMA0SAD_L 0xb0
|
||||
#define REG_OFFSET_DMA0SAD_H 0xb2
|
||||
#define REG_OFFSET_DMA0DAD 0xb4
|
||||
#define REG_OFFSET_DMA0DAD_L 0xb4
|
||||
#define REG_OFFSET_DMA0DAD_H 0xb6
|
||||
#define REG_OFFSET_DMA0CNT 0xb8
|
||||
#define REG_OFFSET_DMA0CNT_L 0xb8
|
||||
#define REG_OFFSET_DMA0CNT_H 0xba
|
||||
#define REG_OFFSET_DMA1 0xbc
|
||||
#define REG_OFFSET_DMA1SAD 0xbc
|
||||
#define REG_OFFSET_DMA1SAD_L 0xbc
|
||||
#define REG_OFFSET_DMA1SAD_H 0xbe
|
||||
#define REG_OFFSET_DMA1DAD 0xc0
|
||||
#define REG_OFFSET_DMA1DAD_L 0xc0
|
||||
#define REG_OFFSET_DMA1DAD_H 0xc2
|
||||
#define REG_OFFSET_DMA1CNT 0xc4
|
||||
#define REG_OFFSET_DMA1CNT_L 0xc4
|
||||
#define REG_OFFSET_DMA1CNT_H 0xc6
|
||||
#define REG_OFFSET_DMA2 0xc8
|
||||
#define REG_OFFSET_DMA2SAD 0xc8
|
||||
#define REG_OFFSET_DMA2SAD_L 0xc8
|
||||
#define REG_OFFSET_DMA2SAD_H 0xca
|
||||
#define REG_OFFSET_DMA2DAD 0xcc
|
||||
#define REG_OFFSET_DMA2DAD_L 0xcc
|
||||
#define REG_OFFSET_DMA2DAD_H 0xce
|
||||
#define REG_OFFSET_DMA2CNT 0xd0
|
||||
#define REG_OFFSET_DMA2CNT_L 0xd0
|
||||
#define REG_OFFSET_DMA2CNT_H 0xd2
|
||||
#define REG_OFFSET_DMA3 0xd4
|
||||
#define REG_OFFSET_DMA3SAD 0xd4
|
||||
#define REG_OFFSET_DMA3SAD_L 0xd4
|
||||
#define REG_OFFSET_DMA3SAD_H 0xd6
|
||||
#define REG_OFFSET_DMA3DAD 0xd8
|
||||
#define REG_OFFSET_DMA3DAD_L 0xd8
|
||||
#define REG_OFFSET_DMA3DAD_H 0xda
|
||||
#define REG_OFFSET_DMA3CNT 0xdc
|
||||
#define REG_OFFSET_DMA3CNT_L 0xdc
|
||||
#define REG_OFFSET_DMA3CNT_H 0xde
|
||||
|
||||
#define REG_OFFSET_TMCNT 0x100
|
||||
#define REG_OFFSET_TMCNT_L 0x100
|
||||
#define REG_OFFSET_TMCNT_H 0x102
|
||||
#define REG_OFFSET_TM0CNT 0x100
|
||||
#define REG_OFFSET_TM0CNT_L 0x100
|
||||
#define REG_OFFSET_TM0CNT_H 0x102
|
||||
#define REG_OFFSET_TM1CNT 0x104
|
||||
#define REG_OFFSET_TM1CNT_L 0x104
|
||||
#define REG_OFFSET_TM1CNT_H 0x106
|
||||
#define REG_OFFSET_TM2CNT 0x108
|
||||
#define REG_OFFSET_TM2CNT_L 0x108
|
||||
#define REG_OFFSET_TM2CNT_H 0x10a
|
||||
#define REG_OFFSET_TM3CNT 0x10c
|
||||
#define REG_OFFSET_TM3CNT_L 0x10c
|
||||
#define REG_OFFSET_TM3CNT_H 0x10e
|
||||
|
||||
#define REG_OFFSET_SIOCNT 0x128
|
||||
#define REG_OFFSET_SIODATA8 0x12a
|
||||
#define REG_OFFSET_SIODATA32 0x120
|
||||
#define REG_OFFSET_SIOMLT_SEND 0x12a
|
||||
#define REG_OFFSET_SIOMLT_RECV 0x120
|
||||
#define REG_OFFSET_SIOMULTI0 0x120
|
||||
#define REG_OFFSET_SIOMULTI1 0x122
|
||||
#define REG_OFFSET_SIOMULTI2 0x124
|
||||
#define REG_OFFSET_SIOMULTI3 0x126
|
||||
|
||||
#define REG_OFFSET_KEYINPUT 0x130
|
||||
#define REG_OFFSET_KEYCNT 0x132
|
||||
|
||||
#define REG_OFFSET_RCNT 0x134
|
||||
|
||||
#define REG_OFFSET_JOYCNT 0x140
|
||||
#define REG_OFFSET_JOYSTAT 0x158
|
||||
#define REG_OFFSET_JOY_RECV 0x150
|
||||
#define REG_OFFSET_JOY_RECV_L 0x150
|
||||
#define REG_OFFSET_JOY_RECV_H 0x152
|
||||
#define REG_OFFSET_JOY_TRANS 0x154
|
||||
#define REG_OFFSET_JOY_TRANS_L 0x154
|
||||
#define REG_OFFSET_JOY_TRANS_H 0x156
|
||||
|
||||
#define REG_OFFSET_IME 0x208
|
||||
#define REG_OFFSET_IE 0x200
|
||||
#define REG_OFFSET_IF 0x202
|
||||
|
||||
#define REG_OFFSET_WAITCNT 0x204
|
||||
|
||||
// I/O register addresses
|
||||
|
||||
#define REG_ADDR_DISPCNT (REG_BASE + REG_OFFSET_DISPCNT)
|
||||
#define REG_ADDR_DISPSTAT (REG_BASE + REG_OFFSET_DISPSTAT)
|
||||
#define REG_ADDR_VCOUNT (REG_BASE + REG_OFFSET_VCOUNT)
|
||||
#define REG_ADDR_BG0CNT (REG_BASE + REG_OFFSET_BG0CNT)
|
||||
#define REG_ADDR_BG1CNT (REG_BASE + REG_OFFSET_BG1CNT)
|
||||
#define REG_ADDR_BG2CNT (REG_BASE + REG_OFFSET_BG2CNT)
|
||||
#define REG_ADDR_BG3CNT (REG_BASE + REG_OFFSET_BG3CNT)
|
||||
#define REG_ADDR_BG0HOFS (REG_BASE + REG_OFFSET_BG0HOFS)
|
||||
#define REG_ADDR_BG0VOFS (REG_BASE + REG_OFFSET_BG0VOFS)
|
||||
#define REG_ADDR_BG1HOFS (REG_BASE + REG_OFFSET_BG1HOFS)
|
||||
#define REG_ADDR_BG1VOFS (REG_BASE + REG_OFFSET_BG1VOFS)
|
||||
#define REG_ADDR_BG2HOFS (REG_BASE + REG_OFFSET_BG2HOFS)
|
||||
#define REG_ADDR_BG2VOFS (REG_BASE + REG_OFFSET_BG2VOFS)
|
||||
#define REG_ADDR_BG3HOFS (REG_BASE + REG_OFFSET_BG3HOFS)
|
||||
#define REG_ADDR_BG3VOFS (REG_BASE + REG_OFFSET_BG3VOFS)
|
||||
#define REG_ADDR_BG2PA (REG_BASE + REG_OFFSET_BG2PA)
|
||||
#define REG_ADDR_BG2PB (REG_BASE + REG_OFFSET_BG2PB)
|
||||
#define REG_ADDR_BG2PC (REG_BASE + REG_OFFSET_BG2PC)
|
||||
#define REG_ADDR_BG2PD (REG_BASE + REG_OFFSET_BG2PD)
|
||||
#define REG_ADDR_BG2X (REG_BASE + REG_OFFSET_BG2X)
|
||||
#define REG_ADDR_BG2X_L (REG_BASE + REG_OFFSET_BG2X_L)
|
||||
#define REG_ADDR_BG2X_H (REG_BASE + REG_OFFSET_BG2X_H)
|
||||
#define REG_ADDR_BG2Y (REG_BASE + REG_OFFSET_BG2Y)
|
||||
#define REG_ADDR_BG2Y_L (REG_BASE + REG_OFFSET_BG2Y_L)
|
||||
#define REG_ADDR_BG2Y_H (REG_BASE + REG_OFFSET_BG2Y_H)
|
||||
#define REG_ADDR_BG3PA (REG_BASE + REG_OFFSET_BG3PA)
|
||||
#define REG_ADDR_BG3PB (REG_BASE + REG_OFFSET_BG3PB)
|
||||
#define REG_ADDR_BG3PC (REG_BASE + REG_OFFSET_BG3PC)
|
||||
#define REG_ADDR_BG3PD (REG_BASE + REG_OFFSET_BG3PD)
|
||||
#define REG_ADDR_BG3X (REG_BASE + REG_OFFSET_BG3X)
|
||||
#define REG_ADDR_BG3X_L (REG_BASE + REG_OFFSET_BG3X_L)
|
||||
#define REG_ADDR_BG3X_H (REG_BASE + REG_OFFSET_BG3X_H)
|
||||
#define REG_ADDR_BG3Y (REG_BASE + REG_OFFSET_BG3Y)
|
||||
#define REG_ADDR_BG3Y_L (REG_BASE + REG_OFFSET_BG3Y_L)
|
||||
#define REG_ADDR_BG3Y_H (REG_BASE + REG_OFFSET_BG3Y_H)
|
||||
#define REG_ADDR_WIN0H (REG_BASE + REG_OFFSET_WIN0H)
|
||||
#define REG_ADDR_WIN1H (REG_BASE + REG_OFFSET_WIN1H)
|
||||
#define REG_ADDR_WIN0V (REG_BASE + REG_OFFSET_WIN0V)
|
||||
#define REG_ADDR_WIN1V (REG_BASE + REG_OFFSET_WIN1V)
|
||||
#define REG_ADDR_WININ (REG_BASE + REG_OFFSET_WININ)
|
||||
#define REG_ADDR_WINOUT (REG_BASE + REG_OFFSET_WINOUT)
|
||||
#define REG_ADDR_MOSAIC (REG_BASE + REG_OFFSET_MOSAIC)
|
||||
#define REG_ADDR_BLDCNT (REG_BASE + REG_OFFSET_BLDCNT)
|
||||
#define REG_ADDR_BLDALPHA (REG_BASE + REG_OFFSET_BLDALPHA)
|
||||
#define REG_ADDR_BLDY (REG_BASE + REG_OFFSET_BLDY)
|
||||
|
||||
#define REG_ADDR_SOUND1CNT_L (REG_BASE + REG_OFFSET_SOUND1CNT_L)
|
||||
#define REG_ADDR_NR10 (REG_BASE + REG_OFFSET_NR10)
|
||||
#define REG_ADDR_SOUND1CNT_H (REG_BASE + REG_OFFSET_SOUND1CNT_H)
|
||||
#define REG_ADDR_NR11 (REG_BASE + REG_OFFSET_NR11)
|
||||
#define REG_ADDR_NR12 (REG_BASE + REG_OFFSET_NR12)
|
||||
#define REG_ADDR_SOUND1CNT_X (REG_BASE + REG_OFFSET_SOUND1CNT_X)
|
||||
#define REG_ADDR_NR13 (REG_BASE + REG_OFFSET_NR13)
|
||||
#define REG_ADDR_NR14 (REG_BASE + REG_OFFSET_NR14)
|
||||
#define REG_ADDR_SOUND2CNT_L (REG_BASE + REG_OFFSET_SOUND2CNT_L)
|
||||
#define REG_ADDR_NR21 (REG_BASE + REG_OFFSET_NR21)
|
||||
#define REG_ADDR_NR22 (REG_BASE + REG_OFFSET_NR22)
|
||||
#define REG_ADDR_SOUND2CNT_H (REG_BASE + REG_OFFSET_SOUND2CNT_H)
|
||||
#define REG_ADDR_NR23 (REG_BASE + REG_OFFSET_NR23)
|
||||
#define REG_ADDR_NR24 (REG_BASE + REG_OFFSET_NR24)
|
||||
#define REG_ADDR_SOUND3CNT_L (REG_BASE + REG_OFFSET_SOUND3CNT_L)
|
||||
#define REG_ADDR_NR30 (REG_BASE + REG_OFFSET_NR30)
|
||||
#define REG_ADDR_SOUND3CNT_H (REG_BASE + REG_OFFSET_SOUND3CNT_H)
|
||||
#define REG_ADDR_NR31 (REG_BASE + REG_OFFSET_NR31)
|
||||
#define REG_ADDR_NR32 (REG_BASE + REG_OFFSET_NR32)
|
||||
#define REG_ADDR_SOUND3CNT_X (REG_BASE + REG_OFFSET_SOUND3CNT_X)
|
||||
#define REG_ADDR_NR33 (REG_BASE + REG_OFFSET_NR33)
|
||||
#define REG_ADDR_NR34 (REG_BASE + REG_OFFSET_NR34)
|
||||
#define REG_ADDR_SOUND4CNT_L (REG_BASE + REG_OFFSET_SOUND4CNT_L)
|
||||
#define REG_ADDR_NR41 (REG_BASE + REG_OFFSET_NR41)
|
||||
#define REG_ADDR_NR42 (REG_BASE + REG_OFFSET_NR42)
|
||||
#define REG_ADDR_SOUND4CNT_H (REG_BASE + REG_OFFSET_SOUND4CNT_H)
|
||||
#define REG_ADDR_NR43 (REG_BASE + REG_OFFSET_NR43)
|
||||
#define REG_ADDR_NR44 (REG_BASE + REG_OFFSET_NR44)
|
||||
#define REG_ADDR_SOUNDCNT_L (REG_BASE + REG_OFFSET_SOUNDCNT_L)
|
||||
#define REG_ADDR_NR50 (REG_BASE + REG_OFFSET_NR50)
|
||||
#define REG_ADDR_NR51 (REG_BASE + REG_OFFSET_NR51)
|
||||
#define REG_ADDR_SOUNDCNT_H (REG_BASE + REG_OFFSET_SOUNDCNT_H)
|
||||
#define REG_ADDR_SOUNDCNT_X (REG_BASE + REG_OFFSET_SOUNDCNT_X)
|
||||
#define REG_ADDR_NR52 (REG_BASE + REG_OFFSET_NR52)
|
||||
#define REG_ADDR_SOUNDBIAS (REG_BASE + REG_OFFSET_SOUNDBIAS)
|
||||
#define REG_ADDR_SOUNDBIAS_L (REG_BASE + REG_OFFSET_SOUNDBIAS_L)
|
||||
#define REG_ADDR_SOUNDBIAS_H (REG_BASE + REG_OFFSET_SOUNDBIAS_H)
|
||||
#define REG_ADDR_WAVE_RAM0 (REG_BASE + REG_OFFSET_WAVE_RAM0)
|
||||
#define REG_ADDR_WAVE_RAM1 (REG_BASE + REG_OFFSET_WAVE_RAM1)
|
||||
#define REG_ADDR_WAVE_RAM2 (REG_BASE + REG_OFFSET_WAVE_RAM2)
|
||||
#define REG_ADDR_WAVE_RAM3 (REG_BASE + REG_OFFSET_WAVE_RAM3)
|
||||
#define REG_ADDR_FIFO_A (REG_BASE + REG_OFFSET_FIFO_A)
|
||||
#define REG_ADDR_FIFO_B (REG_BASE + REG_OFFSET_FIFO_B)
|
||||
|
||||
#define REG_ADDR_DMA0 (REG_BASE + REG_OFFSET_DMA0)
|
||||
#define REG_ADDR_DMA0SAD (REG_BASE + REG_OFFSET_DMA0SAD)
|
||||
#define REG_ADDR_DMA0DAD (REG_BASE + REG_OFFSET_DMA0DAD)
|
||||
#define REG_ADDR_DMA0CNT (REG_BASE + REG_OFFSET_DMA0CNT)
|
||||
#define REG_ADDR_DMA0CNT_L (REG_BASE + REG_OFFSET_DMA0CNT_L)
|
||||
#define REG_ADDR_DMA0CNT_H (REG_BASE + REG_OFFSET_DMA0CNT_H)
|
||||
#define REG_ADDR_DMA1 (REG_BASE + REG_OFFSET_DMA1)
|
||||
#define REG_ADDR_DMA1SAD (REG_BASE + REG_OFFSET_DMA1SAD)
|
||||
#define REG_ADDR_DMA1DAD (REG_BASE + REG_OFFSET_DMA1DAD)
|
||||
#define REG_ADDR_DMA1CNT (REG_BASE + REG_OFFSET_DMA1CNT)
|
||||
#define REG_ADDR_DMA1CNT_L (REG_BASE + REG_OFFSET_DMA1CNT_L)
|
||||
#define REG_ADDR_DMA1CNT_H (REG_BASE + REG_OFFSET_DMA1CNT_H)
|
||||
#define REG_ADDR_DMA2 (REG_BASE + REG_OFFSET_DMA2)
|
||||
#define REG_ADDR_DMA2SAD (REG_BASE + REG_OFFSET_DMA2SAD)
|
||||
#define REG_ADDR_DMA2DAD (REG_BASE + REG_OFFSET_DMA2DAD)
|
||||
#define REG_ADDR_DMA2CNT (REG_BASE + REG_OFFSET_DMA2CNT)
|
||||
#define REG_ADDR_DMA2CNT_L (REG_BASE + REG_OFFSET_DMA2CNT_L)
|
||||
#define REG_ADDR_DMA2CNT_H (REG_BASE + REG_OFFSET_DMA2CNT_H)
|
||||
#define REG_ADDR_DMA3 (REG_BASE + REG_OFFSET_DMA3)
|
||||
#define REG_ADDR_DMA3SAD (REG_BASE + REG_OFFSET_DMA3SAD)
|
||||
#define REG_ADDR_DMA3DAD (REG_BASE + REG_OFFSET_DMA3DAD)
|
||||
#define REG_ADDR_DMA3CNT (REG_BASE + REG_OFFSET_DMA3CNT)
|
||||
#define REG_ADDR_DMA3CNT_L (REG_BASE + REG_OFFSET_DMA3CNT_L)
|
||||
#define REG_ADDR_DMA3CNT_H (REG_BASE + REG_OFFSET_DMA3CNT_H)
|
||||
|
||||
#define REG_ADDR_TMCNT (REG_BASE + REG_OFFSET_TMCNT)
|
||||
#define REG_ADDR_TMCNT_L (REG_BASE + REG_OFFSET_TMCNT_L)
|
||||
#define REG_ADDR_TMCNT_H (REG_BASE + REG_OFFSET_TMCNT_H)
|
||||
#define REG_ADDR_TM0CNT (REG_BASE + REG_OFFSET_TM0CNT)
|
||||
#define REG_ADDR_TM0CNT_L (REG_BASE + REG_OFFSET_TM0CNT_L)
|
||||
#define REG_ADDR_TM0CNT_H (REG_BASE + REG_OFFSET_TM0CNT_H)
|
||||
#define REG_ADDR_TM1CNT (REG_BASE + REG_OFFSET_TM1CNT)
|
||||
#define REG_ADDR_TM1CNT_L (REG_BASE + REG_OFFSET_TM1CNT_L)
|
||||
#define REG_ADDR_TM1CNT_H (REG_BASE + REG_OFFSET_TM1CNT_H)
|
||||
#define REG_ADDR_TM2CNT (REG_BASE + REG_OFFSET_TM2CNT)
|
||||
#define REG_ADDR_TM2CNT_L (REG_BASE + REG_OFFSET_TM2CNT_L)
|
||||
#define REG_ADDR_TM2CNT_H (REG_BASE + REG_OFFSET_TM2CNT_H)
|
||||
#define REG_ADDR_TM3CNT (REG_BASE + REG_OFFSET_TM3CNT)
|
||||
#define REG_ADDR_TM3CNT_L (REG_BASE + REG_OFFSET_TM3CNT_L)
|
||||
#define REG_ADDR_TM3CNT_H (REG_BASE + REG_OFFSET_TM3CNT_H)
|
||||
|
||||
#define REG_ADDR_SIOCNT (REG_BASE + REG_OFFSET_SIOCNT)
|
||||
#define REG_ADDR_SIODATA8 (REG_BASE + REG_OFFSET_SIODATA8)
|
||||
#define REG_ADDR_SIODATA32 (REG_BASE + REG_OFFSET_SIODATA32)
|
||||
#define REG_ADDR_SIOMLT_SEND (REG_BASE + REG_OFFSET_SIOMLT_SEND)
|
||||
#define REG_ADDR_SIOMLT_RECV (REG_BASE + REG_OFFSET_SIOMLT_RECV)
|
||||
#define REG_ADDR_SIOMULTI0 (REG_BASE + REG_OFFSET_SIOMULTI0)
|
||||
#define REG_ADDR_SIOMULTI1 (REG_BASE + REG_OFFSET_SIOMULTI1)
|
||||
#define REG_ADDR_SIOMULTI2 (REG_BASE + REG_OFFSET_SIOMULTI2)
|
||||
#define REG_ADDR_SIOMULTI3 (REG_BASE + REG_OFFSET_SIOMULTI3)
|
||||
|
||||
#define REG_ADDR_KEYINPUT (REG_BASE + REG_OFFSET_KEYINPUT)
|
||||
#define REG_ADDR_KEYCNT (REG_BASE + REG_OFFSET_KEYCNT)
|
||||
|
||||
#define REG_ADDR_RCNT (REG_BASE + REG_OFFSET_RCNT)
|
||||
|
||||
#define REG_ADDR_JOYCNT (REG_BASE + REG_OFFSET_JOYCNT)
|
||||
#define REG_ADDR_JOYSTAT (REG_BASE + REG_OFFSET_JOYSTAT)
|
||||
#define REG_ADDR_JOY_RECV (REG_BASE + REG_OFFSET_JOY_RECV)
|
||||
#define REG_ADDR_JOY_RECV_L (REG_BASE + REG_OFFSET_JOY_RECV_L)
|
||||
#define REG_ADDR_JOY_RECV_H (REG_BASE + REG_OFFSET_JOY_RECV_H)
|
||||
#define REG_ADDR_JOY_TRANS (REG_BASE + REG_OFFSET_JOY_TRANS)
|
||||
#define REG_ADDR_JOY_TRANS_L (REG_BASE + REG_OFFSET_JOY_TRANS_L)
|
||||
#define REG_ADDR_JOY_TRANS_H (REG_BASE + REG_OFFSET_JOY_TRANS_H)
|
||||
|
||||
#define REG_ADDR_IME (REG_BASE + REG_OFFSET_IME)
|
||||
#define REG_ADDR_IE (REG_BASE + REG_OFFSET_IE)
|
||||
#define REG_ADDR_IF (REG_BASE + REG_OFFSET_IF)
|
||||
|
||||
#define REG_ADDR_WAITCNT (REG_BASE + REG_OFFSET_WAITCNT)
|
||||
|
||||
// I/O registers
|
||||
|
||||
#define REG_DISPCNT (*(vu16 *)REG_ADDR_DISPCNT)
|
||||
#define REG_DISPSTAT (*(vu16 *)REG_ADDR_DISPSTAT)
|
||||
#define REG_VCOUNT (*(vu16 *)REG_ADDR_VCOUNT)
|
||||
#define REG_BG0CNT (*(vu16 *)REG_ADDR_BG0CNT)
|
||||
#define REG_BG1CNT (*(vu16 *)REG_ADDR_BG1CNT)
|
||||
#define REG_BG2CNT (*(vu16 *)REG_ADDR_BG2CNT)
|
||||
#define REG_BG3CNT (*(vu16 *)REG_ADDR_BG3CNT)
|
||||
#define REG_BG0HOFS (*(vu16 *)REG_ADDR_BG0HOFS)
|
||||
#define REG_BG0VOFS (*(vu16 *)REG_ADDR_BG0VOFS)
|
||||
#define REG_BG1HOFS (*(vu16 *)REG_ADDR_BG1HOFS)
|
||||
#define REG_BG1VOFS (*(vu16 *)REG_ADDR_BG1VOFS)
|
||||
#define REG_BG2HOFS (*(vu16 *)REG_ADDR_BG2HOFS)
|
||||
#define REG_BG2VOFS (*(vu16 *)REG_ADDR_BG2VOFS)
|
||||
#define REG_BG3HOFS (*(vu16 *)REG_ADDR_BG3HOFS)
|
||||
#define REG_BG3VOFS (*(vu16 *)REG_ADDR_BG3VOFS)
|
||||
#define REG_BG2PA (*(vu16 *)REG_ADDR_BG2PA)
|
||||
#define REG_BG2PB (*(vu16 *)REG_ADDR_BG2PB)
|
||||
#define REG_BG2PC (*(vu16 *)REG_ADDR_BG2PC)
|
||||
#define REG_BG2PD (*(vu16 *)REG_ADDR_BG2PD)
|
||||
#define REG_BG2X (*(vu32 *)REG_ADDR_BG2X)
|
||||
#define REG_BG2X_L (*(vu16 *)REG_ADDR_BG2X_L)
|
||||
#define REG_BG2X_H (*(vu16 *)REG_ADDR_BG2X_H)
|
||||
#define REG_BG2Y (*(vu32 *)REG_ADDR_BG2Y)
|
||||
#define REG_BG2Y_L (*(vu16 *)REG_ADDR_BG2Y_L)
|
||||
#define REG_BG2Y_H (*(vu16 *)REG_ADDR_BG2Y_H)
|
||||
#define REG_BG3PA (*(vu16 *)REG_ADDR_BG3PA)
|
||||
#define REG_BG3PB (*(vu16 *)REG_ADDR_BG3PB)
|
||||
#define REG_BG3PC (*(vu16 *)REG_ADDR_BG3PC)
|
||||
#define REG_BG3PD (*(vu16 *)REG_ADDR_BG3PD)
|
||||
#define REG_BG3X (*(vu32 *)REG_ADDR_BG3X)
|
||||
#define REG_BG3X_L (*(vu16 *)REG_ADDR_BG3X_L)
|
||||
#define REG_BG3X_H (*(vu16 *)REG_ADDR_BG3X_H)
|
||||
#define REG_BG3Y (*(vu32 *)REG_ADDR_BG3Y)
|
||||
#define REG_BG3Y_L (*(vu16 *)REG_ADDR_BG3Y_L)
|
||||
#define REG_BG3Y_H (*(vu16 *)REG_ADDR_BG3Y_H)
|
||||
#define REG_WIN0H (*(vu16 *)REG_ADDR_WIN0H)
|
||||
#define REG_WIN1H (*(vu16 *)REG_ADDR_WIN1H)
|
||||
#define REG_WIN0V (*(vu16 *)REG_ADDR_WIN0V)
|
||||
#define REG_WIN1V (*(vu16 *)REG_ADDR_WIN1V)
|
||||
#define REG_WININ (*(vu16 *)REG_ADDR_WININ)
|
||||
#define REG_WINOUT (*(vu16 *)REG_ADDR_WINOUT)
|
||||
#define REG_MOSAIC (*(vu16 *)REG_ADDR_MOSAIC)
|
||||
#define REG_BLDCNT (*(vu16 *)REG_ADDR_BLDCNT)
|
||||
#define REG_BLDALPHA (*(vu16 *)REG_ADDR_BLDALPHA)
|
||||
#define REG_BLDY (*(vu16 *)REG_ADDR_BLDY)
|
||||
|
||||
#define REG_SOUND1CNT_L (*(vu16 *)REG_ADDR_SOUND1CNT_L)
|
||||
#define REG_NR10 (*(vu8 *)REG_ADDR_NR10)
|
||||
#define REG_SOUND1CNT_H (*(vu16 *)REG_ADDR_SOUND1CNT_H)
|
||||
#define REG_NR11 (*(vu8 *)REG_ADDR_NR11)
|
||||
#define REG_NR12 (*(vu8 *)REG_ADDR_NR12)
|
||||
#define REG_SOUND1CNT_X (*(vu16 *)REG_ADDR_SOUND1CNT_X)
|
||||
#define REG_NR13 (*(vu8 *)REG_ADDR_NR13)
|
||||
#define REG_NR14 (*(vu8 *)REG_ADDR_NR14)
|
||||
#define REG_SOUND2CNT_L (*(vu16 *)REG_ADDR_SOUND2CNT_L)
|
||||
#define REG_NR21 (*(vu8 *)REG_ADDR_NR21)
|
||||
#define REG_NR22 (*(vu8 *)REG_ADDR_NR22)
|
||||
#define REG_SOUND2CNT_H (*(vu16 *)REG_ADDR_SOUND2CNT_H)
|
||||
#define REG_NR23 (*(vu8 *)REG_ADDR_NR23)
|
||||
#define REG_NR24 (*(vu8 *)REG_ADDR_NR24)
|
||||
#define REG_SOUND3CNT_L (*(vu16 *)REG_ADDR_SOUND3CNT_L)
|
||||
#define REG_NR30 (*(vu8 *)REG_ADDR_NR30)
|
||||
#define REG_SOUND3CNT_H (*(vu16 *)REG_ADDR_SOUND3CNT_H)
|
||||
#define REG_NR31 (*(vu8 *)REG_ADDR_NR31)
|
||||
#define REG_NR32 (*(vu8 *)REG_ADDR_NR32)
|
||||
#define REG_SOUND3CNT_X (*(vu16 *)REG_ADDR_SOUND3CNT_X)
|
||||
#define REG_NR33 (*(vu8 *)REG_ADDR_NR33)
|
||||
#define REG_NR34 (*(vu8 *)REG_ADDR_NR34)
|
||||
#define REG_SOUND4CNT_L (*(vu16 *)REG_ADDR_SOUND4CNT_L)
|
||||
#define REG_NR41 (*(vu8 *)REG_ADDR_NR41)
|
||||
#define REG_NR42 (*(vu8 *)REG_ADDR_NR42)
|
||||
#define REG_SOUND4CNT_H (*(vu16 *)REG_ADDR_SOUND4CNT_H)
|
||||
#define REG_NR43 (*(vu8 *)REG_ADDR_NR43)
|
||||
#define REG_NR44 (*(vu8 *)REG_ADDR_NR44)
|
||||
#define REG_SOUNDCNT_L (*(vu16 *)REG_ADDR_SOUNDCNT_L)
|
||||
#define REG_NR50 (*(vu8 *)REG_ADDR_NR50)
|
||||
#define REG_NR51 (*(vu8 *)REG_ADDR_NR51)
|
||||
#define REG_SOUNDCNT_H (*(vu16 *)REG_ADDR_SOUNDCNT_H)
|
||||
#define REG_SOUNDCNT_X (*(vu16 *)REG_ADDR_SOUNDCNT_X)
|
||||
#define REG_NR52 (*(vu8 *)REG_ADDR_NR52)
|
||||
#define REG_SOUNDBIAS (*(vu16 *)REG_ADDR_SOUNDBIAS)
|
||||
#define REG_SOUNDBIAS_L (*(vu8 *)REG_ADDR_SOUNDBIAS_L)
|
||||
#define REG_SOUNDBIAS_H (*(vu8 *)REG_ADDR_SOUNDBIAS_H)
|
||||
#define REG_WAVE_RAM0 (*(vu32 *)REG_ADDR_WAVE_RAM0)
|
||||
#define REG_WAVE_RAM1 (*(vu32 *)REG_ADDR_WAVE_RAM1)
|
||||
#define REG_WAVE_RAM2 (*(vu32 *)REG_ADDR_WAVE_RAM2)
|
||||
#define REG_WAVE_RAM3 (*(vu32 *)REG_ADDR_WAVE_RAM3)
|
||||
#define REG_FIFO_A (*(vu32 *)REG_ADDR_FIFO_A)
|
||||
#define REG_FIFO_B (*(vu32 *)REG_ADDR_FIFO_B)
|
||||
|
||||
#define REG_DMA0SAD (*(vu32 *)REG_ADDR_DMA0SAD)
|
||||
#define REG_DMA0DAD (*(vu32 *)REG_ADDR_DMA0DAD)
|
||||
#define REG_DMA0CNT (*(vu32 *)REG_ADDR_DMA0CNT)
|
||||
#define REG_DMA0CNT_L (*(vu16 *)REG_ADDR_DMA0CNT_L)
|
||||
#define REG_DMA0CNT_H (*(vu16 *)REG_ADDR_DMA0CNT_H)
|
||||
|
||||
#define REG_DMA1SAD (*(vu32 *)REG_ADDR_DMA1SAD)
|
||||
#define REG_DMA1DAD (*(vu32 *)REG_ADDR_DMA1DAD)
|
||||
#define REG_DMA1CNT (*(vu32 *)REG_ADDR_DMA1CNT)
|
||||
#define REG_DMA1CNT_L (*(vu16 *)REG_ADDR_DMA1CNT_L)
|
||||
#define REG_DMA1CNT_H (*(vu16 *)REG_ADDR_DMA1CNT_H)
|
||||
|
||||
#define REG_DMA2SAD (*(vu32 *)REG_ADDR_DMA2SAD)
|
||||
#define REG_DMA2DAD (*(vu32 *)REG_ADDR_DMA2DAD)
|
||||
#define REG_DMA2CNT (*(vu32 *)REG_ADDR_DMA2CNT)
|
||||
#define REG_DMA2CNT_L (*(vu16 *)REG_ADDR_DMA2CNT_L)
|
||||
#define REG_DMA2CNT_H (*(vu16 *)REG_ADDR_DMA2CNT_H)
|
||||
|
||||
#define REG_DMA3SAD (*(vu32 *)REG_ADDR_DMA3SAD)
|
||||
#define REG_DMA3DAD (*(vu32 *)REG_ADDR_DMA3DAD)
|
||||
#define REG_DMA3CNT (*(vu32 *)REG_ADDR_DMA3CNT)
|
||||
#define REG_DMA3CNT_L (*(vu16 *)REG_ADDR_DMA3CNT_L)
|
||||
#define REG_DMA3CNT_H (*(vu16 *)REG_ADDR_DMA3CNT_H)
|
||||
|
||||
#define REG_TMCNT(n) (*(vu16 *)(REG_ADDR_TMCNT + ((n) * 4)))
|
||||
#define REG_TMCNT_L(n) (*(vu16 *)(REG_ADDR_TMCNT_L + ((n) * 4)))
|
||||
#define REG_TMCNT_H(n) (*(vu16 *)(REG_ADDR_TMCNT_H + ((n) * 4)))
|
||||
#define REG_TM0CNT (*(vu32 *)REG_ADDR_TM0CNT)
|
||||
#define REG_TM0CNT_L (*(vu16 *)REG_ADDR_TM0CNT_L)
|
||||
#define REG_TM0CNT_H (*(vu16 *)REG_ADDR_TM0CNT_H)
|
||||
#define REG_TM1CNT (*(vu32 *)REG_ADDR_TM1CNT)
|
||||
#define REG_TM1CNT_L (*(vu16 *)REG_ADDR_TM1CNT_L)
|
||||
#define REG_TM1CNT_H (*(vu16 *)REG_ADDR_TM1CNT_H)
|
||||
#define REG_TM2CNT (*(vu32 *)REG_ADDR_TM2CNT)
|
||||
#define REG_TM2CNT_L (*(vu16 *)REG_ADDR_TM2CNT_L)
|
||||
#define REG_TM2CNT_H (*(vu16 *)REG_ADDR_TM2CNT_H)
|
||||
#define REG_TM3CNT (*(vu32 *)REG_ADDR_TM3CNT)
|
||||
#define REG_TM3CNT_L (*(vu16 *)REG_ADDR_TM3CNT_L)
|
||||
#define REG_TM3CNT_H (*(vu16 *)REG_ADDR_TM3CNT_H)
|
||||
|
||||
#define REG_SIOCNT (*(vu16 *)REG_ADDR_SIOCNT)
|
||||
#define REG_SIODATA8 (*(vu16 *)REG_ADDR_SIODATA8)
|
||||
#define REG_SIODATA32 (*(vu32 *)REG_ADDR_SIODATA32)
|
||||
#define REG_SIOMLT_SEND (*(vu16 *)REG_ADDR_SIOMLT_SEND)
|
||||
#define REG_SIOMLT_RECV (*(vu64 *)REG_ADDR_SIOMLT_RECV)
|
||||
#define REG_SIOMULTI0 (*(vu16 *)REG_ADDR_SIOMULTI0)
|
||||
#define REG_SIOMULTI1 (*(vu16 *)REG_ADDR_SIOMULTI1)
|
||||
#define REG_SIOMULTI2 (*(vu16 *)REG_ADDR_SIOMULTI2)
|
||||
#define REG_SIOMULTI3 (*(vu16 *)REG_ADDR_SIOMULTI3)
|
||||
|
||||
#define REG_KEYINPUT (*(vu16 *)REG_ADDR_KEYINPUT)
|
||||
#define REG_KEYCNT (*(vu16 *)REG_ADDR_KEYCNT)
|
||||
|
||||
#define REG_RCNT (*(vu16 *)REG_ADDR_RCNT)
|
||||
|
||||
#define REG_IME (*(vu16 *)REG_ADDR_IME)
|
||||
#define REG_IE (*(vu16 *)REG_ADDR_IE)
|
||||
#define REG_IF (*(vu16 *)REG_ADDR_IF)
|
||||
|
||||
#define REG_WAITCNT (*(vu16 *)REG_ADDR_WAITCNT)
|
||||
|
||||
// I/O register fields
|
||||
|
||||
// DISPCNT
|
||||
#define DISPCNT_MODE_0 0x0000 // BG0: text, BG1: text, BG2: text, BG3: text
|
||||
#define DISPCNT_MODE_1 0x0001 // BG0: text, BG1: text, BG2: affine, BG3: off
|
||||
#define DISPCNT_MODE_2 0x0002 // BG0: off, BG1: off, BG2: affine, BG3: affine
|
||||
#define DISPCNT_MODE_3 0x0003 // Bitmap mode, 240x160, BGR555 color
|
||||
#define DISPCNT_MODE_4 0x0004 // Bitmap mode, 240x160, 256 color palette
|
||||
#define DISPCNT_MODE_5 0x0005 // Bitmap mode, 160x128, BGR555 color
|
||||
#define DISPCNT_HBLANK_INTERVAL 0x0020 // Allow access to OAM during H-Blank
|
||||
#define DISPCNT_OBJ_1D_MAP 0x0040
|
||||
#define DISPCNT_FORCED_BLANK 0x0080
|
||||
#define DISPCNT_BG0_ON 0x0100
|
||||
#define DISPCNT_BG1_ON 0x0200
|
||||
#define DISPCNT_BG2_ON 0x0400
|
||||
#define DISPCNT_BG3_ON 0x0800
|
||||
#define DISPCNT_BG_ALL_ON 0x0F00
|
||||
#define DISPCNT_OBJ_ON 0x1000
|
||||
#define DISPCNT_WIN0_ON 0x2000
|
||||
#define DISPCNT_WIN1_ON 0x4000
|
||||
#define DISPCNT_OBJWIN_ON 0x8000
|
||||
|
||||
// DISPSTAT
|
||||
#define DISPSTAT_VBLANK 0x0001 // in V-Blank
|
||||
#define DISPSTAT_HBLANK 0x0002 // in H-Blank
|
||||
#define DISPSTAT_VCOUNT 0x0004 // V-Count match
|
||||
#define DISPSTAT_VBLANK_INTR 0x0008 // V-Blank interrupt enabled
|
||||
#define DISPSTAT_HBLANK_INTR 0x0010 // H-Blank interrupt enabled
|
||||
#define DISPSTAT_VCOUNT_INTR 0x0020 // V-Count interrupt enabled
|
||||
|
||||
// BGCNT
|
||||
#define BGCNT_PRIORITY(n) (n) // Values 0 - 3. Lower priority BGs will be drawn on top of higher priority BGs.
|
||||
#define BGCNT_CHARBASE(n) ((n) << 2) // Values 0 - 3. Base block for tile pixel data.
|
||||
#define BGCNT_MOSAIC 0x0040
|
||||
#define BGCNT_16COLOR 0x0000 // 4 bits per pixel
|
||||
#define BGCNT_256COLOR 0x0080 // 8 bits per pixel
|
||||
#define BGCNT_SCREENBASE(n) ((n) << 8) // Values 0 - 31. Base block for tile map.
|
||||
#define BGCNT_WRAP 0x2000 // Only affects affine BGs. Text BGs wrap by default.
|
||||
#define BGCNT_TXT256x256 0x0000 // Internal screen size size of text mode BG in pixels.
|
||||
#define BGCNT_TXT512x256 0x4000
|
||||
#define BGCNT_TXT256x512 0x8000
|
||||
#define BGCNT_TXT512x512 0xC000
|
||||
#define BGCNT_AFF128x128 0x0000 // Internal screen size size of affine mode BG in pixels.
|
||||
#define BGCNT_AFF256x256 0x4000
|
||||
#define BGCNT_AFF512x512 0x8000
|
||||
#define BGCNT_AFF1024x1024 0xC000
|
||||
|
||||
// WININ/OUT
|
||||
#define WININ_WIN0_BG0 (1 << 0)
|
||||
#define WININ_WIN0_BG1 (1 << 1)
|
||||
#define WININ_WIN0_BG2 (1 << 2)
|
||||
#define WININ_WIN0_BG3 (1 << 3)
|
||||
#define WININ_WIN0_BG_ALL (WININ_WIN0_BG0 | WININ_WIN0_BG1 | WININ_WIN0_BG2 | WININ_WIN0_BG3)
|
||||
#define WININ_WIN0_OBJ (1 << 4)
|
||||
#define WININ_WIN0_CLR (1 << 5)
|
||||
#define WININ_WIN1_BG0 (1 << 8)
|
||||
#define WININ_WIN1_BG1 (1 << 9)
|
||||
#define WININ_WIN1_BG2 (1 << 10)
|
||||
#define WININ_WIN1_BG3 (1 << 11)
|
||||
#define WININ_WIN1_BG_ALL (WININ_WIN1_BG0 | WININ_WIN1_BG1 | WININ_WIN1_BG2 | WININ_WIN1_BG3)
|
||||
#define WININ_WIN1_OBJ (1 << 12)
|
||||
#define WININ_WIN1_CLR (1 << 13)
|
||||
|
||||
#define WINOUT_WIN01_BG0 (1 << 0)
|
||||
#define WINOUT_WIN01_BG1 (1 << 1)
|
||||
#define WINOUT_WIN01_BG2 (1 << 2)
|
||||
#define WINOUT_WIN01_BG3 (1 << 3)
|
||||
#define WINOUT_WIN01_BG_ALL (WINOUT_WIN01_BG0 | WINOUT_WIN01_BG1 | WINOUT_WIN01_BG2 | WINOUT_WIN01_BG3)
|
||||
#define WINOUT_WIN01_OBJ (1 << 4)
|
||||
#define WINOUT_WIN01_CLR (1 << 5)
|
||||
#define WINOUT_WINOBJ_BG0 (1 << 8)
|
||||
#define WINOUT_WINOBJ_BG1 (1 << 9)
|
||||
#define WINOUT_WINOBJ_BG2 (1 << 10)
|
||||
#define WINOUT_WINOBJ_BG3 (1 << 11)
|
||||
#define WINOUT_WINOBJ_BG_ALL (WINOUT_WINOBJ_BG0 | WINOUT_WINOBJ_BG1 | WINOUT_WINOBJ_BG2 | WINOUT_WINOBJ_BG3)
|
||||
#define WINOUT_WINOBJ_OBJ (1 << 12)
|
||||
#define WINOUT_WINOBJ_CLR (1 << 13)
|
||||
|
||||
#define WIN_RANGE(a, b) (((a) << 8) | (b))
|
||||
#define WIN_RANGE2(a, b) ((b) | ((a) << 8))
|
||||
|
||||
// BLDCNT
|
||||
// Bits 0-5 select layers for the 1st target
|
||||
#define BLDCNT_TGT1_BG0 (1 << 0)
|
||||
#define BLDCNT_TGT1_BG1 (1 << 1)
|
||||
#define BLDCNT_TGT1_BG2 (1 << 2)
|
||||
#define BLDCNT_TGT1_BG3 (1 << 3)
|
||||
#define BLDCNT_TGT1_OBJ (1 << 4)
|
||||
#define BLDCNT_TGT1_BD (1 << 5)
|
||||
#define BLDCNT_TGT1_ALL (BLDCNT_TGT1_BG0 | BLDCNT_TGT1_BG1 | BLDCNT_TGT1_BG2 | BLDCNT_TGT1_BG3 | BLDCNT_TGT1_OBJ | BLDCNT_TGT1_BD)
|
||||
// Bits 6-7 select the special effect
|
||||
#define BLDCNT_EFFECT_NONE (0 << 6) // no special effect
|
||||
#define BLDCNT_EFFECT_BLEND (1 << 6) // 1st+2nd targets mixed (controlled by BLDALPHA)
|
||||
#define BLDCNT_EFFECT_LIGHTEN (2 << 6) // 1st target becomes whiter (controlled by BLDY)
|
||||
#define BLDCNT_EFFECT_DARKEN (3 << 6) // 1st target becomes blacker (controlled by BLDY)
|
||||
// Bits 8-13 select layers for the 2nd target
|
||||
#define BLDCNT_TGT2_BG0 (1 << 8)
|
||||
#define BLDCNT_TGT2_BG1 (1 << 9)
|
||||
#define BLDCNT_TGT2_BG2 (1 << 10)
|
||||
#define BLDCNT_TGT2_BG3 (1 << 11)
|
||||
#define BLDCNT_TGT2_OBJ (1 << 12)
|
||||
#define BLDCNT_TGT2_BD (1 << 13)
|
||||
#define BLDCNT_TGT2_ALL (BLDCNT_TGT2_BG0 | BLDCNT_TGT2_BG1 | BLDCNT_TGT2_BG2 | BLDCNT_TGT2_BG3 | BLDCNT_TGT2_OBJ | BLDCNT_TGT2_BD)
|
||||
|
||||
// BLDALPHA
|
||||
#define BLDALPHA_BLEND(target1, target2) (((target2) << 8) | (target1))
|
||||
|
||||
// SOUNDCNT_H
|
||||
#define SOUND_CGB_MIX_QUARTER 0x0000
|
||||
#define SOUND_CGB_MIX_HALF 0x0001
|
||||
#define SOUND_CGB_MIX_FULL 0x0002
|
||||
#define SOUND_A_MIX_HALF 0x0000
|
||||
#define SOUND_A_MIX_FULL 0x0004
|
||||
#define SOUND_B_MIX_HALF 0x0000
|
||||
#define SOUND_B_MIX_FULL 0x0008
|
||||
#define SOUND_ALL_MIX_FULL 0x000E
|
||||
#define SOUND_A_RIGHT_OUTPUT 0x0100
|
||||
#define SOUND_A_LEFT_OUTPUT 0x0200
|
||||
#define SOUND_A_TIMER_0 0x0000
|
||||
#define SOUND_A_TIMER_1 0x0400
|
||||
#define SOUND_A_FIFO_RESET 0x0800
|
||||
#define SOUND_B_RIGHT_OUTPUT 0x1000
|
||||
#define SOUND_B_LEFT_OUTPUT 0x2000
|
||||
#define SOUND_B_TIMER_0 0x0000
|
||||
#define SOUND_B_TIMER_1 0x4000
|
||||
#define SOUND_B_FIFO_RESET 0x8000
|
||||
|
||||
// SOUNDCNT_X
|
||||
#define SOUND_1_ON 0x0001
|
||||
#define SOUND_2_ON 0x0002
|
||||
#define SOUND_3_ON 0x0004
|
||||
#define SOUND_4_ON 0x0008
|
||||
#define SOUND_MASTER_ENABLE 0x0080
|
||||
|
||||
// DMA
|
||||
#define DMA_DEST_INC 0x0000
|
||||
#define DMA_DEST_DEC 0x0020
|
||||
#define DMA_DEST_FIXED 0x0040
|
||||
#define DMA_DEST_RELOAD 0x0060
|
||||
#define DMA_SRC_INC 0x0000
|
||||
#define DMA_SRC_DEC 0x0080
|
||||
#define DMA_SRC_FIXED 0x0100
|
||||
#define DMA_REPEAT 0x0200
|
||||
#define DMA_16BIT 0x0000
|
||||
#define DMA_32BIT 0x0400
|
||||
#define DMA_DREQ_ON 0x0800
|
||||
#define DMA_START_NOW 0x0000
|
||||
#define DMA_START_VBLANK 0x1000
|
||||
#define DMA_START_HBLANK 0x2000
|
||||
#define DMA_START_SPECIAL 0x3000
|
||||
#define DMA_START_MASK 0x3000
|
||||
#define DMA_INTR_ENABLE 0x4000
|
||||
#define DMA_ENABLE 0x8000
|
||||
|
||||
// timer
|
||||
#define TIMER_1CLK 0x00
|
||||
#define TIMER_64CLK 0x01
|
||||
#define TIMER_256CLK 0x02
|
||||
#define TIMER_1024CLK 0x03
|
||||
#define TIMER_INTR_ENABLE 0x40
|
||||
#define TIMER_ENABLE 0x80
|
||||
|
||||
// serial
|
||||
#define SIO_ID 0x0030 // Communication ID
|
||||
|
||||
#define SIO_8BIT_MODE 0x0000 // Normal 8-bit communication mode
|
||||
#define SIO_32BIT_MODE 0x1000 // Normal 32-bit communication mode
|
||||
#define SIO_MULTI_MODE 0x2000 // Multi-player communication mode
|
||||
#define SIO_UART_MODE 0x3000 // UART communication mode
|
||||
|
||||
#define SIO_9600_BPS 0x0000 // baud rate 9600 bps
|
||||
#define SIO_38400_BPS 0x0001 // 38400 bps
|
||||
#define SIO_57600_BPS 0x0002 // 57600 bps
|
||||
#define SIO_115200_BPS 0x0003 // 115200 bps
|
||||
|
||||
#define SIO_MULTI_SI 0x0004 // Multi-player communication SI terminal
|
||||
#define SIO_MULTI_SD 0x0008 // SD terminal
|
||||
#define SIO_MULTI_BUSY 0x0080
|
||||
|
||||
#define SIO_ERROR 0x0040 // Detect error
|
||||
#define SIO_START 0x0080 // Start transfer
|
||||
#define SIO_ENABLE 0x0080 // Enable SIO
|
||||
|
||||
#define SIO_INTR_ENABLE 0x4000
|
||||
|
||||
#define SIO_MULTI_SI_SHIFT 2
|
||||
#define SIO_MULTI_SI_MASK 0x1
|
||||
#define SIO_MULTI_DI_SHIFT 3
|
||||
#define SIO_MULTI_DI_MASK 0x1
|
||||
|
||||
// keys
|
||||
#define A_BUTTON 0x0001
|
||||
#define B_BUTTON 0x0002
|
||||
#define SELECT_BUTTON 0x0004
|
||||
#define START_BUTTON 0x0008
|
||||
#define DPAD_RIGHT 0x0010
|
||||
#define DPAD_LEFT 0x0020
|
||||
#define DPAD_UP 0x0040
|
||||
#define DPAD_DOWN 0x0080
|
||||
#define R_BUTTON 0x0100
|
||||
#define L_BUTTON 0x0200
|
||||
#define KEYS_MASK 0x03FF
|
||||
#define KEY_INTR_ENABLE 0x0400
|
||||
#define KEY_OR_INTR 0x0000
|
||||
#define KEY_AND_INTR 0x8000
|
||||
#define DPAD_ANY ((DPAD_RIGHT | DPAD_LEFT | DPAD_UP | DPAD_DOWN))
|
||||
#define JOY_EXCL_DPAD 0x030F
|
||||
|
||||
// interrupt flags
|
||||
#define INTR_FLAG_VBLANK (1 << 0)
|
||||
#define INTR_FLAG_HBLANK (1 << 1)
|
||||
#define INTR_FLAG_VCOUNT (1 << 2)
|
||||
#define INTR_FLAG_TIMER0 (1 << 3)
|
||||
#define INTR_FLAG_TIMER1 (1 << 4)
|
||||
#define INTR_FLAG_TIMER2 (1 << 5)
|
||||
#define INTR_FLAG_TIMER3 (1 << 6)
|
||||
#define INTR_FLAG_SERIAL (1 << 7)
|
||||
#define INTR_FLAG_DMA0 (1 << 8)
|
||||
#define INTR_FLAG_DMA1 (1 << 9)
|
||||
#define INTR_FLAG_DMA2 (1 << 10)
|
||||
#define INTR_FLAG_DMA3 (1 << 11)
|
||||
#define INTR_FLAG_KEYPAD (1 << 12)
|
||||
#define INTR_FLAG_GAMEPAK (1 << 13)
|
||||
|
||||
// WAITCNT
|
||||
#define WAITCNT_SRAM_4 (0 << 0)
|
||||
#define WAITCNT_SRAM_3 (1 << 0)
|
||||
#define WAITCNT_SRAM_2 (2 << 0)
|
||||
#define WAITCNT_SRAM_8 (3 << 0)
|
||||
#define WAITCNT_SRAM_MASK (3 << 0)
|
||||
|
||||
#define WAITCNT_WS0_N_4 (0 << 2)
|
||||
#define WAITCNT_WS0_N_3 (1 << 2)
|
||||
#define WAITCNT_WS0_N_2 (2 << 2)
|
||||
#define WAITCNT_WS0_N_8 (3 << 2)
|
||||
#define WAITCNT_WS0_N_MASK (3 << 2)
|
||||
|
||||
#define WAITCNT_WS0_S_2 (0 << 4)
|
||||
#define WAITCNT_WS0_S_1 (1 << 4)
|
||||
|
||||
#define WAITCNT_WS1_N_4 (0 << 5)
|
||||
#define WAITCNT_WS1_N_3 (1 << 5)
|
||||
#define WAITCNT_WS1_N_2 (2 << 5)
|
||||
#define WAITCNT_WS1_N_8 (3 << 5)
|
||||
#define WAITCNT_WS1_N_MASK (3 << 5)
|
||||
|
||||
#define WAITCNT_WS1_S_4 (0 << 7)
|
||||
#define WAITCNT_WS1_S_1 (1 << 7)
|
||||
|
||||
#define WAITCNT_WS2_N_4 (0 << 8)
|
||||
#define WAITCNT_WS2_N_3 (1 << 8)
|
||||
#define WAITCNT_WS2_N_2 (2 << 8)
|
||||
#define WAITCNT_WS2_N_8 (3 << 8)
|
||||
#define WAITCNT_WS2_N_MASK (3 << 8)
|
||||
|
||||
#define WAITCNT_WS2_S_8 (0 << 10)
|
||||
#define WAITCNT_WS2_S_1 (1 << 10)
|
||||
|
||||
#define WAITCNT_PHI_OUT_NONE (0 << 11)
|
||||
#define WAITCNT_PHI_OUT_4MHZ (1 << 11)
|
||||
#define WAITCNT_PHI_OUT_8MHZ (2 << 11)
|
||||
#define WAITCNT_PHI_OUT_16MHZ (3 << 11)
|
||||
#define WAITCNT_PHI_OUT_MASK (3 << 11)
|
||||
|
||||
#define WAITCNT_PREFETCH_ENABLE (1 << 14)
|
||||
|
||||
#define WAITCNT_AGB (0 << 15)
|
||||
#define WAITCNT_CGB (1 << 15)
|
||||
|
||||
#endif // GUARD_GBA_IO_REG_H
|
||||
@@ -0,0 +1,50 @@
|
||||
#ifndef GUARD_GBA_ISAGBPRINT_H
|
||||
#define GUARD_GBA_ISAGBPRINT_H
|
||||
|
||||
#ifdef NDEBUG
|
||||
#define AGBPrintInit()
|
||||
#define AGBPutc(cChr)
|
||||
#define AGBPrint(pBuf)
|
||||
#define AGBPrintf(pBuf, ...)
|
||||
#define AGBPrintFlush1Block()
|
||||
#define AGBPrintFlush()
|
||||
#define AGBAssert(pFile, nLine, pExpression, nStopProgram)
|
||||
#else
|
||||
void AGBPrintInit(void);
|
||||
void AGBPutc(const char cChr);
|
||||
void AGBPrint(const char *pBuf);
|
||||
void AGBPrintf(const char *pBuf, ...);
|
||||
void AGBPrintFlush1Block(void);
|
||||
void AGBPrintFlush(void);
|
||||
void AGBAssert(const char *pFile, int nLine, const char *pExpression, int nStopProgram);
|
||||
#endif
|
||||
|
||||
#undef AGB_ASSERT
|
||||
#ifdef NDEBUG
|
||||
#define AGB_ASSERT(exp)
|
||||
#else
|
||||
#define AGB_ASSERT(exp) (exp) ? ((void*)0) : AGBAssert(__FILE__, __LINE__, #exp, 1);
|
||||
#endif
|
||||
|
||||
#undef AGB_WARNING
|
||||
#ifdef NDEBUG
|
||||
#define AGB_WARNING(exp)
|
||||
#else
|
||||
#define AGB_WARNING(exp) (exp) ? ((void*)0) : AGBAssert(__FILE__, __LINE__, #exp, 0);
|
||||
#endif
|
||||
|
||||
// for matching purposes
|
||||
|
||||
#ifdef NDEBUG
|
||||
#define AGB_ASSERT_EX(exp, file, line)
|
||||
#else
|
||||
#define AGB_ASSERT_EX(exp, file, line) (exp) ? ((void*)0) : AGBAssert(file, line, #exp, 1);
|
||||
#endif
|
||||
|
||||
#ifdef NDEBUG
|
||||
#define AGB_WARNING_EX(exp, file, line)
|
||||
#else
|
||||
#define AGB_WARNING_EX(exp, file, line) (exp) ? ((void*)0) : AGBAssert(file, line, #exp, 0);
|
||||
#endif
|
||||
|
||||
#endif // GUARD_GBA_ISAGBPRINT_H
|
||||
@@ -0,0 +1,467 @@
|
||||
#ifndef GUARD_GBA_M4A_INTERNAL_H
|
||||
#define GUARD_GBA_M4A_INTERNAL_H
|
||||
|
||||
#include "gba/gba.h"
|
||||
|
||||
// ASCII encoding of 'Smsh' in reverse
|
||||
// This is presumably short for SMASH, the developer of MKS4AGB.
|
||||
#define ID_NUMBER 0x68736D53
|
||||
|
||||
#define C_V 0x40 // center value for PAN, BEND, and TUNE
|
||||
|
||||
#define SOUND_MODE_REVERB_VAL 0x0000007F
|
||||
#define SOUND_MODE_REVERB_SET 0x00000080
|
||||
#define SOUND_MODE_MAXCHN 0x00000F00
|
||||
#define SOUND_MODE_MAXCHN_SHIFT 8
|
||||
#define SOUND_MODE_MASVOL 0x0000F000
|
||||
#define SOUND_MODE_MASVOL_SHIFT 12
|
||||
#define SOUND_MODE_FREQ_05734 0x00010000
|
||||
#define SOUND_MODE_FREQ_07884 0x00020000
|
||||
#define SOUND_MODE_FREQ_10512 0x00030000
|
||||
#define SOUND_MODE_FREQ_13379 0x00040000
|
||||
#define SOUND_MODE_FREQ_15768 0x00050000
|
||||
#define SOUND_MODE_FREQ_18157 0x00060000
|
||||
#define SOUND_MODE_FREQ_21024 0x00070000
|
||||
#define SOUND_MODE_FREQ_26758 0x00080000
|
||||
#define SOUND_MODE_FREQ_31536 0x00090000
|
||||
#define SOUND_MODE_FREQ_36314 0x000A0000
|
||||
#define SOUND_MODE_FREQ_40137 0x000B0000
|
||||
#define SOUND_MODE_FREQ_42048 0x000C0000
|
||||
#define SOUND_MODE_FREQ 0x000F0000
|
||||
#define SOUND_MODE_FREQ_SHIFT 16
|
||||
#define SOUND_MODE_DA_BIT_9 0x00800000
|
||||
#define SOUND_MODE_DA_BIT_8 0x00900000
|
||||
#define SOUND_MODE_DA_BIT_7 0x00A00000
|
||||
#define SOUND_MODE_DA_BIT_6 0x00B00000
|
||||
#define SOUND_MODE_DA_BIT 0x00B00000
|
||||
#define SOUND_MODE_DA_BIT_SHIFT 20
|
||||
|
||||
struct WaveData
|
||||
{
|
||||
u16 type;
|
||||
u16 status;
|
||||
u32 freq;
|
||||
u32 loopStart;
|
||||
u32 size; // number of samples
|
||||
s8 data[1]; // samples
|
||||
};
|
||||
|
||||
#define TONEDATA_TYPE_CGB 0x07
|
||||
#define TONEDATA_TYPE_FIX 0x08
|
||||
#define TONEDATA_TYPE_SPL 0x40 // key split
|
||||
#define TONEDATA_TYPE_RHY 0x80 // rhythm
|
||||
|
||||
#define TONEDATA_P_S_PAN 0xc0
|
||||
#define TONEDATA_P_S_PAM TONEDATA_P_S_PAN
|
||||
|
||||
struct ToneData
|
||||
{
|
||||
u8 type;
|
||||
u8 key;
|
||||
u8 length; // sound length (compatible sound)
|
||||
u8 pan_sweep; // pan or sweep (compatible sound ch. 1)
|
||||
struct WaveData *wav;
|
||||
u8 attack;
|
||||
u8 decay;
|
||||
u8 sustain;
|
||||
u8 release;
|
||||
};
|
||||
|
||||
struct CgbChannel
|
||||
{
|
||||
u8 sf;
|
||||
u8 ty;
|
||||
u8 rightVolume;
|
||||
u8 leftVolume;
|
||||
u8 at;
|
||||
u8 de;
|
||||
u8 su;
|
||||
u8 re;
|
||||
u8 ky;
|
||||
u8 ev;
|
||||
u8 eg;
|
||||
u8 ec;
|
||||
u8 echoVolume;
|
||||
u8 echoLength;
|
||||
u8 d1;
|
||||
u8 d2;
|
||||
u8 gt;
|
||||
u8 mk;
|
||||
u8 ve;
|
||||
u8 pr;
|
||||
u8 rp;
|
||||
u8 d3[3];
|
||||
u8 d5;
|
||||
u8 sg;
|
||||
u8 n4;
|
||||
u8 pan;
|
||||
u8 panMask;
|
||||
u8 mo;
|
||||
u8 le;
|
||||
u8 sw;
|
||||
u32 fr;
|
||||
u32 wp;
|
||||
u32 cp;
|
||||
u32 tp;
|
||||
u32 pp;
|
||||
u32 np;
|
||||
u8 d4[8];
|
||||
};
|
||||
|
||||
struct MusicPlayerTrack;
|
||||
|
||||
struct SoundChannel
|
||||
{
|
||||
u8 status;
|
||||
u8 type;
|
||||
u8 rightVolume;
|
||||
u8 leftVolume;
|
||||
u8 attack;
|
||||
u8 decay;
|
||||
u8 sustain;
|
||||
u8 release;
|
||||
u8 ky;
|
||||
u8 ev;
|
||||
u8 er;
|
||||
u8 el;
|
||||
u8 echoVolume;
|
||||
u8 echoLength;
|
||||
u8 d1;
|
||||
u8 d2;
|
||||
u8 gt;
|
||||
u8 mk;
|
||||
u8 ve;
|
||||
u8 pr;
|
||||
u8 rp;
|
||||
u8 d3[3];
|
||||
u32 ct;
|
||||
u32 fw;
|
||||
u32 freq;
|
||||
struct WaveData *wav;
|
||||
u32 cp;
|
||||
struct MusicPlayerTrack *track;
|
||||
u32 pp;
|
||||
u32 np;
|
||||
u32 d4;
|
||||
u16 xpi;
|
||||
u16 xpc;
|
||||
};
|
||||
|
||||
#define MAX_DIRECTSOUND_CHANNELS 12
|
||||
|
||||
#define PCM_DMA_BUF_SIZE 1584 // size of Direct Sound buffer
|
||||
|
||||
struct SoundInfo
|
||||
{
|
||||
// This field is normally equal to ID_NUMBER but it is set to other
|
||||
// values during sensitive operations for locking purposes.
|
||||
// This field should be volatile but isn't. This could potentially cause
|
||||
// race conditions.
|
||||
u32 ident;
|
||||
|
||||
vu8 pcmDmaCounter;
|
||||
|
||||
// Direct Sound
|
||||
u8 reverb;
|
||||
u8 maxChans;
|
||||
u8 masterVolume;
|
||||
u8 freq;
|
||||
|
||||
u8 mode;
|
||||
u8 c15;
|
||||
u8 pcmDmaPeriod; // number of V-blanks per PCM DMA
|
||||
u8 maxLines;
|
||||
u8 gap[3];
|
||||
s32 pcmSamplesPerVBlank;
|
||||
s32 pcmFreq;
|
||||
s32 divFreq;
|
||||
struct CgbChannel *cgbChans;
|
||||
u32 func;
|
||||
u32 intp;
|
||||
void (*CgbSound)(void);
|
||||
void (*CgbOscOff)(u8);
|
||||
u32 (*MidiKeyToCgbFreq)(u8, u8, u8);
|
||||
u32 MPlayJumpTable;
|
||||
u32 plynote;
|
||||
u32 ExtVolPit;
|
||||
u8 gap2[16];
|
||||
struct SoundChannel chans[MAX_DIRECTSOUND_CHANNELS];
|
||||
s8 pcmBuffer[PCM_DMA_BUF_SIZE * 2];
|
||||
};
|
||||
|
||||
struct SongHeader
|
||||
{
|
||||
u8 trackCount;
|
||||
u8 blockCount;
|
||||
u8 priority;
|
||||
u8 reverb;
|
||||
struct ToneData *tone;
|
||||
u8 *part[1];
|
||||
};
|
||||
|
||||
struct PokemonCrySong
|
||||
{
|
||||
u8 trackCount;
|
||||
u8 blockCount;
|
||||
u8 priority;
|
||||
u8 reverb;
|
||||
struct ToneData *tone;
|
||||
u8 *part[2];
|
||||
u8 gap;
|
||||
u8 part0; // 0x11
|
||||
u8 tuneValue; // 0x12
|
||||
u8 gotoCmd; // 0x13
|
||||
u32 gotoTarget; // 0x14
|
||||
u8 part1; // 0x18
|
||||
u8 tuneValue2; // 0x19
|
||||
u8 cont[2]; // 0x1A
|
||||
u8 volCmd; // 0x1C
|
||||
u8 volumeValue; // 0x1D
|
||||
u8 unkCmd0D[2]; // 0x1E
|
||||
u32 unkCmd0DParam; // 0x20
|
||||
u8 xreleCmd[2]; // 0x24
|
||||
u8 releaseValue; // 0x26
|
||||
u8 panCmd;
|
||||
u8 panValue; // 0x28
|
||||
u8 tieCmd; // 0x29
|
||||
u8 tieKeyValue; // 0x2A
|
||||
u8 tieVelocityValue; // 0x2B
|
||||
u8 unkCmd0C[2]; // 0x2C
|
||||
u16 unkCmd0CParam; // 0x2E
|
||||
u8 end[2]; // 0x30
|
||||
};
|
||||
|
||||
#define MPT_FLG_VOLSET 0x01
|
||||
#define MPT_FLG_VOLCHG 0x03
|
||||
#define MPT_FLG_PITSET 0x04
|
||||
#define MPT_FLG_PITCHG 0x0C
|
||||
#define MPT_FLG_START 0x40
|
||||
#define MPT_FLG_EXIST 0x80
|
||||
|
||||
struct MusicPlayerTrack
|
||||
{
|
||||
u8 flags;
|
||||
u8 wait;
|
||||
u8 patternLevel;
|
||||
u8 repN;
|
||||
u8 gateTime;
|
||||
u8 key;
|
||||
u8 velocity;
|
||||
u8 runningStatus;
|
||||
u8 keyM;
|
||||
u8 pitM;
|
||||
s8 keyShift;
|
||||
s8 keyShiftX;
|
||||
s8 tune;
|
||||
u8 pitX;
|
||||
s8 bend;
|
||||
u8 bendRange;
|
||||
u8 volMR;
|
||||
u8 volML;
|
||||
u8 vol;
|
||||
u8 volX;
|
||||
s8 pan;
|
||||
s8 panX;
|
||||
s8 modM;
|
||||
u8 mod;
|
||||
u8 modT;
|
||||
u8 lfoSpeed;
|
||||
u8 lfoSpeedC;
|
||||
u8 lfoDelay;
|
||||
u8 lfoDelayC;
|
||||
u8 priority;
|
||||
u8 echoVolume;
|
||||
u8 echoLength;
|
||||
struct SoundChannel *chan;
|
||||
struct ToneData tone;
|
||||
u8 gap[10];
|
||||
u16 unk_3A;
|
||||
u32 unk_3C;
|
||||
u8 *cmdPtr;
|
||||
u8 *patternStack[3];
|
||||
};
|
||||
|
||||
#define MUSICPLAYER_STATUS_TRACK 0x0000ffff
|
||||
#define MUSICPLAYER_STATUS_PAUSE 0x80000000
|
||||
|
||||
#define MAX_MUSICPLAYER_TRACKS 16
|
||||
|
||||
#define TEMPORARY_FADE 0x0001
|
||||
#define FADE_IN 0x0002
|
||||
#define FADE_VOL_MAX 64
|
||||
#define FADE_VOL_SHIFT 2
|
||||
|
||||
struct MusicPlayerInfo
|
||||
{
|
||||
struct SongHeader *songHeader;
|
||||
u32 status;
|
||||
u8 trackCount;
|
||||
u8 priority;
|
||||
u8 cmd;
|
||||
u8 unk_B;
|
||||
u32 clock;
|
||||
u8 gap[8];
|
||||
u8 *memAccArea;
|
||||
u16 tempoD;
|
||||
u16 tempoU;
|
||||
u16 tempoI;
|
||||
u16 tempoC;
|
||||
u16 fadeOI;
|
||||
u16 fadeOC;
|
||||
u16 fadeOV;
|
||||
struct MusicPlayerTrack *tracks;
|
||||
struct ToneData *tone;
|
||||
u32 ident;
|
||||
u32 func;
|
||||
u32 intp;
|
||||
};
|
||||
|
||||
struct MusicPlayer
|
||||
{
|
||||
struct MusicPlayerInfo *info;
|
||||
struct MusicPlayerTrack *track;
|
||||
u8 unk_8;
|
||||
u16 unk_A;
|
||||
};
|
||||
|
||||
struct Song
|
||||
{
|
||||
struct SongHeader *header;
|
||||
u16 ms;
|
||||
u16 me;
|
||||
};
|
||||
|
||||
extern const struct MusicPlayer gMPlayTable[];
|
||||
extern const struct Song gSongTable[];
|
||||
|
||||
|
||||
|
||||
extern u8 gMPlayMemAccArea[];
|
||||
|
||||
//u8 gPokemonCrySong[52];
|
||||
//u8 gPokemonCrySongs[52 * MAX_POKEMON_CRIES];
|
||||
|
||||
#define MAX_POKEMON_CRIES 2
|
||||
|
||||
extern struct PokemonCrySong gPokemonCrySong;
|
||||
extern struct PokemonCrySong gPokemonCrySongs[];
|
||||
|
||||
extern struct MusicPlayerInfo gPokemonCryMusicPlayers[];
|
||||
extern struct MusicPlayerTrack gPokemonCryTracks[];
|
||||
|
||||
extern char SoundMainRAM[];
|
||||
|
||||
extern void *gMPlayJumpTable[];
|
||||
|
||||
typedef void (*XcmdFunc)(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
extern const XcmdFunc gXcmdTable[];
|
||||
|
||||
extern struct CgbChannel gCgbChans[];
|
||||
|
||||
extern const u8 gScaleTable[];
|
||||
extern const u32 gFreqTable[];
|
||||
extern const u16 gPcmSamplesPerVBlankTable[];
|
||||
|
||||
extern const u8 gCgbScaleTable[];
|
||||
extern const s16 gCgbFreqTable[];
|
||||
extern const u8 gNoiseTable[];
|
||||
|
||||
extern const struct PokemonCrySong gPokemonCrySongTemplate;
|
||||
|
||||
extern const struct ToneData voicegroup000;
|
||||
|
||||
extern char gNumMusicPlayers[];
|
||||
extern char gMaxLines[];
|
||||
|
||||
#define NUM_MUSIC_PLAYERS ((u16)gNumMusicPlayers)
|
||||
#define MAX_LINES ((u32)gMaxLines)
|
||||
|
||||
u32 umul3232H32(u32 multiplier, u32 multiplicand);
|
||||
void SoundMain(void);
|
||||
void SoundMainBTM(void);
|
||||
void TrackStop(struct MusicPlayerInfo *mplayInfo, struct MusicPlayerTrack *track);
|
||||
void MPlayMain(void);
|
||||
void RealClearChain(void *x);
|
||||
|
||||
void MPlayContinue(struct MusicPlayerInfo *mplayInfo);
|
||||
void MPlayStart(struct MusicPlayerInfo *mplayInfo, struct SongHeader *songHeader);
|
||||
void m4aMPlayStop(struct MusicPlayerInfo *mplayInfo);
|
||||
void FadeOutBody(struct MusicPlayerInfo *mplayInfo);
|
||||
void TrkVolPitSet(struct MusicPlayerInfo *mplayInfo, struct MusicPlayerTrack *track);
|
||||
void MPlayFadeOut(struct MusicPlayerInfo *mplayInfo, u16 speed);
|
||||
void ClearChain(void *x);
|
||||
void Clear64byte(void *addr);
|
||||
void SoundInit(struct SoundInfo *soundInfo);
|
||||
void MPlayExtender(struct CgbChannel *cgbChans);
|
||||
void m4aSoundMode(u32 mode);
|
||||
void MPlayOpen(struct MusicPlayerInfo *mplayInfo, struct MusicPlayerTrack *track, u8 a3);
|
||||
void CgbSound(void);
|
||||
void CgbOscOff(u8);
|
||||
u32 MidiKeyToCgbFreq(u8, u8, u8);
|
||||
void DummyFunc(void);
|
||||
void MPlayJumpTableCopy(void **mplayJumpTable);
|
||||
void SampleFreqSet(u32 freq);
|
||||
void m4aSoundVSyncOn(void);
|
||||
void m4aSoundVSyncOff(void);
|
||||
|
||||
void m4aMPlayTempoControl(struct MusicPlayerInfo *mplayInfo, u16 tempo);
|
||||
void m4aMPlayVolumeControl(struct MusicPlayerInfo *mplayInfo, u16 trackBits, u16 volume);
|
||||
void m4aMPlayPitchControl(struct MusicPlayerInfo *mplayInfo, u16 trackBits, s16 pitch);
|
||||
void m4aMPlayPanpotControl(struct MusicPlayerInfo *mplayInfo, u16 trackBits, s8 pan);
|
||||
void ClearModM(struct MusicPlayerTrack *track);
|
||||
void m4aMPlayModDepthSet(struct MusicPlayerInfo *mplayInfo, u16 trackBits, u8 modDepth);
|
||||
void m4aMPlayLFOSpeedSet(struct MusicPlayerInfo *mplayInfo, u16 trackBits, u8 lfoSpeed);
|
||||
|
||||
struct MusicPlayerInfo *SetPokemonCryTone(struct ToneData *tone);
|
||||
void SetPokemonCryVolume(u8 val);
|
||||
void SetPokemonCryPanpot(s8 val);
|
||||
void SetPokemonCryPitch(s16 val);
|
||||
void SetPokemonCryLength(u16 val);
|
||||
void SetPokemonCryRelease(u8 val);
|
||||
void SetPokemonCryProgress(u32 val);
|
||||
int IsPokemonCryPlaying(struct MusicPlayerInfo *mplayInfo);
|
||||
void SetPokemonCryChorus(s8 val);
|
||||
void SetPokemonCryStereo(u32 val);
|
||||
void SetPokemonCryPriority(u8 val);
|
||||
|
||||
// sound command handler functions
|
||||
void ply_fine(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_goto(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_patt(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_pend(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_rept(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_memacc(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_prio(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_tempo(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_keysh(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_voice(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_vol(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_pan(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_bend(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_bendr(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_lfos(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_lfodl(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_mod(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_modt(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_tune(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_port(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xcmd(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_endtie(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_note(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
|
||||
// extended sound command handler functions
|
||||
void ply_xxx(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xwave(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xtype(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xatta(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xdeca(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xsust(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xrele(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xiecv(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xiecl(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xleng(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xswee(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xcmd_0C(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
void ply_xcmd_0D(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
|
||||
|
||||
#endif // GUARD_GBA_M4A_INTERNAL_H
|
||||
@@ -0,0 +1,247 @@
|
||||
#ifndef GUARD_GBA_MACRO_H
|
||||
#define GUARD_GBA_MACRO_H
|
||||
|
||||
#define CPU_FILL(value, dest, size, bit) \
|
||||
{ \
|
||||
vu##bit tmp = (vu##bit)(value); \
|
||||
CpuSet((void *)&tmp, \
|
||||
dest, \
|
||||
CPU_SET_##bit##BIT | CPU_SET_SRC_FIXED | ((size)/(bit/8) & 0x1FFFFF)); \
|
||||
}
|
||||
|
||||
#define CpuFill16(value, dest, size) CPU_FILL(value, dest, size, 16)
|
||||
#define CpuFill32(value, dest, size) CPU_FILL(value, dest, size, 32)
|
||||
|
||||
#define CPU_COPY(src, dest, size, bit) CpuSet(src, dest, CPU_SET_##bit##BIT | ((size)/(bit/8) & 0x1FFFFF))
|
||||
|
||||
#define CpuCopy16(src, dest, size) CPU_COPY(src, dest, size, 16)
|
||||
#define CpuCopy32(src, dest, size) CPU_COPY(src, dest, size, 32)
|
||||
|
||||
#define CpuFastFill(value, dest, size) \
|
||||
{ \
|
||||
vu32 tmp = (vu32)(value); \
|
||||
CpuFastSet((void *)&tmp, \
|
||||
dest, \
|
||||
CPU_FAST_SET_SRC_FIXED | ((size)/(32/8) & 0x1FFFFF)); \
|
||||
}
|
||||
|
||||
#define CpuFastFill16(value, dest, size) CpuFastFill(((value) << 16) | (value), (dest), (size))
|
||||
|
||||
#define CpuFastFill8(value, dest, size) CpuFastFill(((value) << 24) | ((value) << 16) | ((value) << 8) | (value), (dest), (size))
|
||||
|
||||
#define CpuFastCopy(src, dest, size) CpuFastSet(src, dest, ((size)/(32/8) & 0x1FFFFF))
|
||||
|
||||
#define DmaSet(dmaNum, src, dest, control) \
|
||||
{ \
|
||||
vu32 *dmaRegs = (vu32 *)REG_ADDR_DMA##dmaNum; \
|
||||
dmaRegs[0] = (vu32)(src); \
|
||||
dmaRegs[1] = (vu32)(dest); \
|
||||
dmaRegs[2] = (vu32)(control); \
|
||||
dmaRegs[2]; \
|
||||
}
|
||||
|
||||
#define DMA_FILL(dmaNum, value, dest, size, bit) \
|
||||
{ \
|
||||
vu##bit tmp = (vu##bit)(value); \
|
||||
DmaSet(dmaNum, \
|
||||
&tmp, \
|
||||
dest, \
|
||||
(DMA_ENABLE | DMA_START_NOW | DMA_##bit##BIT | DMA_SRC_FIXED | DMA_DEST_INC) << 16 \
|
||||
| ((size)/(bit/8))); \
|
||||
}
|
||||
|
||||
#define DmaFill16(dmaNum, value, dest, size) DMA_FILL(dmaNum, value, dest, size, 16)
|
||||
#define DmaFill32(dmaNum, value, dest, size) DMA_FILL(dmaNum, value, dest, size, 32)
|
||||
|
||||
// Note that the DMA clear macros cause the DMA control value to be calculated
|
||||
// at runtime rather than compile time. The size is divided by the DMA transfer
|
||||
// unit size (2 or 4 bytes) and then combined with the DMA control flags using a
|
||||
// bitwise OR operation.
|
||||
|
||||
#define DMA_CLEAR(dmaNum, dest, size, bit) \
|
||||
{ \
|
||||
vu##bit *_dest = (vu##bit *)(dest); \
|
||||
u32 _size = size; \
|
||||
DmaFill##bit(dmaNum, 0, _dest, _size); \
|
||||
}
|
||||
|
||||
#define DmaClear16(dmaNum, dest, size) DMA_CLEAR(dmaNum, dest, size, 16)
|
||||
#define DmaClear32(dmaNum, dest, size) DMA_CLEAR(dmaNum, dest, size, 32)
|
||||
|
||||
#define DMA_COPY(dmaNum, src, dest, size, bit) \
|
||||
DmaSet(dmaNum, \
|
||||
src, \
|
||||
dest, \
|
||||
(DMA_ENABLE | DMA_START_NOW | DMA_##bit##BIT | DMA_SRC_INC | DMA_DEST_INC) << 16 \
|
||||
| ((size)/(bit/8)))
|
||||
|
||||
#define DmaCopy16(dmaNum, src, dest, size) DMA_COPY(dmaNum, src, dest, size, 16)
|
||||
#define DmaCopy32(dmaNum, src, dest, size) DMA_COPY(dmaNum, src, dest, size, 32)
|
||||
|
||||
#define DmaCopyLarge(dmaNum, src, dest, size, block, bit) \
|
||||
{ \
|
||||
const void *_src = src; \
|
||||
void *_dest = (void *)dest; \
|
||||
u32 _size = size; \
|
||||
while (1) \
|
||||
{ \
|
||||
DmaCopy##bit(dmaNum, _src, _dest, (block)); \
|
||||
_src += (block); \
|
||||
_dest += (block); \
|
||||
_size -= (block); \
|
||||
if (_size <= (block)) \
|
||||
{ \
|
||||
DmaCopy##bit(dmaNum, _src, _dest, _size); \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#define DmaCopyLarge16(dmaNum, src, dest, size, block) DmaCopyLarge(dmaNum, src, dest, size, block, 16)
|
||||
|
||||
#define DmaCopyLarge32(dmaNum, src, dest, size, block) DmaCopyLarge(dmaNum, src, dest, size, block, 32)
|
||||
|
||||
#define DmaFillLarge(dmaNum, value, dest, size, block, bit) \
|
||||
{ \
|
||||
void *_dest = (void *)dest; \
|
||||
u32 _size = size; \
|
||||
while (1) \
|
||||
{ \
|
||||
DmaFill##bit(dmaNum, value, _dest, (block)); \
|
||||
_dest += (block); \
|
||||
_size -= (block); \
|
||||
if (_size <= (block)) \
|
||||
{ \
|
||||
DmaFill##bit(dmaNum, value, _dest, _size); \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#define DmaFillLarge16(dmaNum, value, dest, size, block) DmaFillLarge(dmaNum, value, dest, size, block, 16)
|
||||
|
||||
#define DmaFillLarge32(dmaNum, value, dest, size, block) DmaFillLarge(dmaNum, value, dest, size, block, 32)
|
||||
|
||||
#define DmaClearLarge(dmaNum, dest, size, block, bit) \
|
||||
{ \
|
||||
void *_dest = (void *)dest; \
|
||||
u32 _size = size; \
|
||||
while (1) \
|
||||
{ \
|
||||
DmaFill##bit(dmaNum, 0, _dest, (block)); \
|
||||
_dest += (block); \
|
||||
_size -= (block); \
|
||||
if (_size <= (block)) \
|
||||
{ \
|
||||
DmaFill##bit(dmaNum, 0, _dest, _size); \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#define DmaClearLarge16(dmaNum, dest, size, block) DmaClearLarge(dmaNum, dest, size, block, 16)
|
||||
|
||||
#define DmaClearLarge32(dmaNum, dest, size, block) DmaClearLarge(dmaNum, dest, size, block, 32)
|
||||
|
||||
#define DmaCopyDefvars(dmaNum, src, dest, size, bit) \
|
||||
{ \
|
||||
const void *_src = src; \
|
||||
void *_dest = (void *)(dest); \
|
||||
u32 _size = size; \
|
||||
DmaCopy##bit(dmaNum, _src, _dest, _size); \
|
||||
}
|
||||
|
||||
#define DmaCopy16Defvars(dmaNum, src, dest, size) DmaCopyDefvars(dmaNum, src, dest, size, 16)
|
||||
#define DmaCopy32Defvars(dmaNum, src, dest, size) DmaCopyDefvars(dmaNum, src, dest, size, 32)
|
||||
|
||||
#define DmaFillDefvars(dmaNum, value, dest, size, bit) \
|
||||
{ \
|
||||
void *_dest = (void *)dest; \
|
||||
u32 _size = size; \
|
||||
DmaFill##bit(dmaNum, value, _dest, _size); \
|
||||
}
|
||||
|
||||
#define DmaFill16Defvars(dmaNum, value, dest, size) DmaFillDefvars(dmaNum, value, dest, size, 16)
|
||||
#define DmaFill32Defvars(dmaNum, value, dest, size) DmaFillDefvars(dmaNum, value, dest, size, 32)
|
||||
|
||||
#define DmaClearDefvars(dmaNum, dest, size, bit) \
|
||||
{ \
|
||||
void *_dest = (void *)dest; \
|
||||
u32 _size = size; \
|
||||
DmaClear##bit(dmaNum, _dest, _size); \
|
||||
}
|
||||
|
||||
#define DmaClear16Defvars(dmaNum, dest, size) DmaClearDefvars(dmaNum, dest, size, 16)
|
||||
#define DmaClear32Defvars(dmaNum, dest, size) DmaClearDefvars(dmaNum, dest, size, 32)
|
||||
|
||||
#define DmaStop(dmaNum) \
|
||||
{ \
|
||||
vu16 *dmaRegs = (vu16 *)REG_ADDR_DMA##dmaNum; \
|
||||
dmaRegs[5] &= ~(DMA_START_MASK | DMA_DREQ_ON | DMA_REPEAT); \
|
||||
dmaRegs[5] &= ~DMA_ENABLE; \
|
||||
dmaRegs[5]; \
|
||||
}
|
||||
|
||||
#define IntrEnable(flags) \
|
||||
{ \
|
||||
u16 imeTemp; \
|
||||
\
|
||||
imeTemp = REG_IME; \
|
||||
REG_IME = 0; \
|
||||
REG_IE |= flags; \
|
||||
REG_IME = imeTemp; \
|
||||
} \
|
||||
// from pokeemerald
|
||||
// Maximum amount of data we will transfer in one operation
|
||||
#define MAX_DMA_BLOCK_SIZE 0x1000
|
||||
|
||||
#define MAX_DMA_REQUESTS 128
|
||||
|
||||
#define DMA_REQUEST_COPY32 1
|
||||
#define DMA_REQUEST_FILL32 2
|
||||
#define DMA_REQUEST_COPY16 3
|
||||
#define DMA_REQUEST_FILL16 4
|
||||
|
||||
#define Dma3CopyLarge_(src, dest, size, bit) \
|
||||
{ \
|
||||
const void *_src = src; \
|
||||
void *_dest = (void *)dest; \
|
||||
u32 _size = size; \
|
||||
while (1) \
|
||||
{ \
|
||||
if (_size <= MAX_DMA_BLOCK_SIZE) \
|
||||
{ \
|
||||
DmaCopy##bit(3, _src, _dest, _size); \
|
||||
break; \
|
||||
} \
|
||||
DmaCopy##bit(3, _src, _dest, MAX_DMA_BLOCK_SIZE); \
|
||||
_src += MAX_DMA_BLOCK_SIZE; \
|
||||
_dest += MAX_DMA_BLOCK_SIZE; \
|
||||
_size -= MAX_DMA_BLOCK_SIZE; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define Dma3CopyLarge16_(src, dest, size) Dma3CopyLarge_(src, dest, size, 16)
|
||||
#define Dma3CopyLarge32_(src, dest, size) Dma3CopyLarge_(src, dest, size, 32)
|
||||
|
||||
#define Dma3FillLarge_(value, dest, size, bit) \
|
||||
{ \
|
||||
void *_dest = (void *)dest; \
|
||||
u32 _size = size; \
|
||||
while (1) \
|
||||
{ \
|
||||
if (_size <= MAX_DMA_BLOCK_SIZE) \
|
||||
{ \
|
||||
DmaFill##bit(3, value, _dest, _size); \
|
||||
break; \
|
||||
} \
|
||||
DmaFill##bit(3, value, _dest, MAX_DMA_BLOCK_SIZE); \
|
||||
_dest += MAX_DMA_BLOCK_SIZE; \
|
||||
_size -= MAX_DMA_BLOCK_SIZE; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define Dma3FillLarge16_(value, dest, size) Dma3FillLarge_(value, dest, size, 16)
|
||||
#define Dma3FillLarge32_(value, dest, size) Dma3FillLarge_(value, dest, size, 32)
|
||||
|
||||
#endif // GUARD_GBA_MACRO_H
|
||||
@@ -0,0 +1,55 @@
|
||||
#ifndef GUARD_GBA_MULTIBOOT_H
|
||||
#define GUARD_GBA_MULTIBOOT_H
|
||||
|
||||
#define MULTIBOOT_NCHILD 3 // Maximum number of slaves
|
||||
#define MULTIBOOT_HEADER_SIZE 0xc0 // Header size
|
||||
#define MULTIBOOT_SEND_SIZE_MIN 0x100 // Minimum transmission size
|
||||
#define MULTIBOOT_SEND_SIZE_MAX 0x40000 // Maximum transmission size
|
||||
|
||||
struct MultiBootParam
|
||||
{
|
||||
u32 system_work[5]; // 00
|
||||
u8 handshake_data; // 14
|
||||
u8 padding; // 15
|
||||
u16 handshake_timeout; // 16
|
||||
u8 probe_count; // 18
|
||||
u8 client_data[MULTIBOOT_NCHILD]; // 19
|
||||
u8 palette_data; // 1c
|
||||
u8 response_bit; // 1d
|
||||
u8 client_bit; // 1e
|
||||
u8 reserved1; // 1f
|
||||
const u8 *boot_srcp; // 20
|
||||
const u8 *boot_endp; // 24
|
||||
const u8 *masterp;
|
||||
u8 *reserved2[MULTIBOOT_NCHILD];
|
||||
u32 system_work2[4];
|
||||
u8 sendflag;
|
||||
u8 probe_target_bit;
|
||||
u8 check_wait;
|
||||
u8 server_type;
|
||||
};
|
||||
|
||||
#define MULTIBOOT_ERROR_04 0x04
|
||||
#define MULTIBOOT_ERROR_08 0x08
|
||||
#define MULTIBOOT_ERROR_0c 0x0c
|
||||
#define MULTIBOOT_ERROR_40 0x40
|
||||
#define MULTIBOOT_ERROR_44 0x44
|
||||
#define MULTIBOOT_ERROR_48 0x48
|
||||
#define MULTIBOOT_ERROR_4c 0x4c
|
||||
#define MULTIBOOT_ERROR_80 0x80
|
||||
#define MULTIBOOT_ERROR_84 0x84
|
||||
#define MULTIBOOT_ERROR_88 0x88
|
||||
#define MULTIBOOT_ERROR_8c 0x8c
|
||||
#define MULTIBOOT_ERROR_NO_PROBE_TARGET 0x50
|
||||
#define MULTIBOOT_ERROR_NO_DLREADY 0x60
|
||||
#define MULTIBOOT_ERROR_BOOT_FAILURE 0x70
|
||||
#define MULTIBOOT_ERROR_HANDSHAKE_FAILURE 0x71
|
||||
|
||||
#define MULTIBOOT_CONNECTION_CHECK_WAIT 15
|
||||
|
||||
#define MULTIBOOT_SERVER_TYPE_NORMAL 0
|
||||
#define MULTIBOOT_SERVER_TYPE_QUICK 1
|
||||
|
||||
#define MULTIBOOT_HANDSHAKE_TIMEOUT 400
|
||||
|
||||
#endif // GUARD_GBA_MULTIBOOT_H
|
||||
@@ -0,0 +1,57 @@
|
||||
#ifndef GUARD_GBA_SYSCALL_H
|
||||
#define GUARD_GBA_SYSCALL_H
|
||||
|
||||
#include "gba/types.h"
|
||||
|
||||
#define RESET_EWRAM 0x01
|
||||
#define RESET_IWRAM 0x02
|
||||
#define RESET_PALETTE 0x04
|
||||
#define RESET_VRAM 0x08
|
||||
#define RESET_OAM 0x10
|
||||
#define RESET_SIO_REGS 0x20
|
||||
#define RESET_SOUND_REGS 0x40
|
||||
#define RESET_REGS 0x80
|
||||
#define RESET_ALL 0xFF
|
||||
|
||||
void SoftReset(u32 resetFlags);
|
||||
|
||||
void RegisterRamReset(u32 resetFlags);
|
||||
|
||||
void VBlankIntrWait(void);
|
||||
|
||||
u16 Sqrt(u32 num);
|
||||
|
||||
u16 ArcTan2(s16 x, s16 y);
|
||||
|
||||
#define CPU_SET_SRC_FIXED 0x01000000
|
||||
#define CPU_SET_16BIT 0x00000000
|
||||
#define CPU_SET_32BIT 0x04000000
|
||||
|
||||
void CpuSet(const void *src, void *dest, u32 control);
|
||||
|
||||
#define CPU_FAST_SET_SRC_FIXED 0x01000000
|
||||
|
||||
void CpuFastSet(const void *src, void *dest, u32 control);
|
||||
|
||||
void BgAffineSet(struct BgAffineSrcData *src, struct BgAffineDstData *dest, s32 count);
|
||||
|
||||
void ObjAffineSet(struct ObjAffineSrcData *src, void *dest, s32 count, s32 offset);
|
||||
|
||||
void LZ77UnCompWram(const void *src, void *dest);
|
||||
|
||||
void LZ77UnCompVram(const void *src, void *dest);
|
||||
|
||||
void RLUnCompWram(const void *src, void *dest);
|
||||
|
||||
void RLUnCompVram(const void *src, void *dest);
|
||||
|
||||
int MultiBoot(struct MultiBootParam *mp);
|
||||
|
||||
void SoundBiasReset(void);
|
||||
|
||||
void SoundBiasSet(void);
|
||||
|
||||
u32 Div(u32 divisor, u32 dividend);
|
||||
u32 Mod(u32 divisor, u32 dividend);
|
||||
|
||||
#endif // GUARD_GBA_SYSCALL_H
|
||||
@@ -0,0 +1,146 @@
|
||||
#ifndef GUARD_GBA_TYPES_H
|
||||
#define GUARD_GBA_TYPES_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
typedef uint64_t u64;
|
||||
typedef int8_t s8;
|
||||
typedef int16_t s16;
|
||||
typedef int32_t s32;
|
||||
typedef int64_t s64;
|
||||
|
||||
typedef volatile u8 vu8;
|
||||
typedef volatile u16 vu16;
|
||||
typedef volatile u32 vu32;
|
||||
typedef volatile u64 vu64;
|
||||
typedef volatile s8 vs8;
|
||||
typedef volatile s16 vs16;
|
||||
typedef volatile s32 vs32;
|
||||
typedef volatile s64 vs64;
|
||||
|
||||
typedef float f32;
|
||||
typedef double f64;
|
||||
|
||||
typedef u8 bool8;
|
||||
typedef u16 bool16;
|
||||
typedef u32 bool32;
|
||||
|
||||
struct BgCnt
|
||||
{
|
||||
u16 priority:2;
|
||||
u16 charBaseBlock:2;
|
||||
u16 dummy:2;
|
||||
u16 mosaic:1;
|
||||
u16 palettes:1;
|
||||
u16 screenBaseBlock:5;
|
||||
u16 areaOverflowMode:1;
|
||||
u16 screenSize:2;
|
||||
};
|
||||
typedef volatile struct BgCnt vBgCnt;
|
||||
|
||||
struct PlttData
|
||||
{
|
||||
u16 r:5; // red
|
||||
u16 g:5; // green
|
||||
u16 b:5; // blue
|
||||
u16 unused_15:1;
|
||||
};
|
||||
|
||||
struct OamData
|
||||
{
|
||||
/*0x00*/ u32 y:8;
|
||||
/*0x01*/ u32 affineMode:2; // 0x1, 0x2 -> 0x4
|
||||
u32 objMode:2; // 0x4, 0x8 -> 0xC
|
||||
u32 mosaic:1; // 0x10
|
||||
u32 bpp:1; // 0x20
|
||||
u32 shape:2; // 0x40, 0x80 -> 0xC0
|
||||
|
||||
/*0x02*/ u32 x:9;
|
||||
u32 matrixNum:5; // bits 3/4 are h-flip/v-flip if not in affine mode
|
||||
u32 size:2;
|
||||
|
||||
/*0x04*/ u16 tileNum:10; // 0x3FF
|
||||
u16 priority:2; // 0x400, 0x800 -> 0xC00
|
||||
u16 paletteNum:4;
|
||||
/*0x06*/ u16 affineParam;
|
||||
};
|
||||
|
||||
#define ST_OAM_OBJ_NORMAL 0
|
||||
#define ST_OAM_OBJ_BLEND 1
|
||||
#define ST_OAM_OBJ_WINDOW 2
|
||||
|
||||
#define ST_OAM_AFFINE_OFF 0
|
||||
#define ST_OAM_AFFINE_NORMAL 1
|
||||
#define ST_OAM_AFFINE_ERASE 2
|
||||
#define ST_OAM_AFFINE_DOUBLE 3
|
||||
|
||||
#define ST_OAM_AFFINE_ON_MASK 1
|
||||
#define ST_OAM_AFFINE_DOUBLE_MASK 2
|
||||
|
||||
#define ST_OAM_4BPP 0
|
||||
#define ST_OAM_8BPP 1
|
||||
|
||||
#define ST_OAM_SQUARE 0
|
||||
#define ST_OAM_H_RECTANGLE 1
|
||||
#define ST_OAM_V_RECTANGLE 2
|
||||
|
||||
struct BgAffineSrcData
|
||||
{
|
||||
s32 texX;
|
||||
s32 texY;
|
||||
s16 scrX;
|
||||
s16 scrY;
|
||||
s16 sx;
|
||||
s16 sy;
|
||||
u16 alpha;
|
||||
};
|
||||
|
||||
struct BgAffineDstData
|
||||
{
|
||||
s16 pa;
|
||||
s16 pb;
|
||||
s16 pc;
|
||||
s16 pd;
|
||||
s32 dx;
|
||||
s32 dy;
|
||||
};
|
||||
|
||||
struct ObjAffineSrcData
|
||||
{
|
||||
s16 xScale;
|
||||
s16 yScale;
|
||||
u16 rotation;
|
||||
};
|
||||
|
||||
// Multi-player SIO Control Structure
|
||||
struct SioMultiCnt
|
||||
{
|
||||
u16 baudRate:2; // baud rate
|
||||
u16 si:1; // SI terminal
|
||||
u16 sd:1; // SD terminal
|
||||
u16 id:2; // ID
|
||||
u16 error:1; // error flag
|
||||
u16 enable:1; // SIO enable
|
||||
u16 unused_11_8:4;
|
||||
u16 mode:2; // communication mode (should equal 2)
|
||||
u16 intrEnable:1; // IRQ enable
|
||||
u16 unused_15:1;
|
||||
u16 data; // data
|
||||
};
|
||||
|
||||
#define ST_SIO_MULTI_MODE 2 // Multi-player communication mode
|
||||
|
||||
// baud rate
|
||||
#define ST_SIO_9600_BPS 0 // 9600 bps
|
||||
#define ST_SIO_38400_BPS 1 // 38400 bps
|
||||
#define ST_SIO_57600_BPS 2 // 57600 bps
|
||||
#define ST_SIO_115200_BPS 3 // 115200 bps
|
||||
|
||||
typedef void (*MainCallback)(void);
|
||||
typedef void (*IntrCallback)(void);
|
||||
typedef void (*IntrFunc)(void);
|
||||
|
||||
#endif // GUARD_GBA_TYPES_H
|
||||
@@ -1,7 +1,7 @@
|
||||
#ifndef GUARD_GLOBAL_H
|
||||
#define GUARD_GLOBAL_H
|
||||
|
||||
#include <gba/gba.h>
|
||||
#include "gba/gba.h"
|
||||
|
||||
// global.h from pokemon ruby
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#ifndef GUARD_MAIN_H
|
||||
#define GUARD_MAIN_H
|
||||
|
||||
#include <gba/gba.h>
|
||||
#include "gba/gba.h"
|
||||
|
||||
enum RomHeaderValidationResult
|
||||
{
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
#ifndef GUARD_RTC_H
|
||||
#define GUARD_RTC_H
|
||||
|
||||
#include <gba/gba.h>
|
||||
#include <siirtc.h>
|
||||
#include "gba/gba.h"
|
||||
#include "siirtc.h"
|
||||
#include "global.h"
|
||||
|
||||
extern struct Time gTimeSinceBerryUpdate;
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
#ifndef GUARD_RTC_H
|
||||
#define GUARD_RTC_H
|
||||
|
||||
#include "gba/gba.h"
|
||||
|
||||
#define SIIRTCINFO_INTFE 0x01 // frequency interrupt enable
|
||||
#define SIIRTCINFO_INTME 0x02 // per-minute interrupt enable
|
||||
#define SIIRTCINFO_INTAE 0x04 // alarm interrupt enable
|
||||
#define SIIRTCINFO_24HOUR 0x40 // 0: 12-hour mode, 1: 24-hour mode
|
||||
#define SIIRTCINFO_POWER 0x80 // power on or power failure occurred
|
||||
|
||||
enum
|
||||
{
|
||||
MONTH_JAN = 1,
|
||||
MONTH_FEB,
|
||||
MONTH_MAR,
|
||||
MONTH_APR,
|
||||
MONTH_MAY,
|
||||
MONTH_JUN,
|
||||
MONTH_JUL,
|
||||
MONTH_AUG,
|
||||
MONTH_SEP,
|
||||
MONTH_OCT,
|
||||
MONTH_NOV,
|
||||
MONTH_DEC
|
||||
};
|
||||
|
||||
struct SiiRtcInfo
|
||||
{
|
||||
u8 year;
|
||||
u8 month;
|
||||
u8 day;
|
||||
u8 dayOfWeek;
|
||||
u8 hour;
|
||||
u8 minute;
|
||||
u8 second;
|
||||
u8 status;
|
||||
u8 alarmHour;
|
||||
u8 alarmMinute;
|
||||
};
|
||||
|
||||
void SiiRtcUnprotect(void);
|
||||
void SiiRtcProtect(void);
|
||||
u8 SiiRtcProbe(void);
|
||||
bool8 SiiRtcReset(void);
|
||||
bool8 SiiRtcGetStatus(struct SiiRtcInfo *rtc);
|
||||
bool8 SiiRtcSetStatus(struct SiiRtcInfo *rtc);
|
||||
bool8 SiiRtcGetDateTime(struct SiiRtcInfo *rtc);
|
||||
bool8 SiiRtcSetDateTime(struct SiiRtcInfo *rtc);
|
||||
bool8 SiiRtcGetTime(struct SiiRtcInfo *rtc);
|
||||
bool8 SiiRtcSetTime(struct SiiRtcInfo *rtc);
|
||||
bool8 SiiRtcSetAlarm(struct SiiRtcInfo *rtc);
|
||||
|
||||
#endif // GUARD_RTC_H
|
||||
@@ -15,26 +15,11 @@ SECTIONS {
|
||||
lib_text :
|
||||
ALIGN(4)
|
||||
{
|
||||
*libagb_flash.a:agb_flash.o(.text);
|
||||
*libagb_flash.a:agb_flash_1m.o(.text);
|
||||
*libagb_flash.a:agb_flash_mx.o(.text);
|
||||
*libagbsyscall.a:ArcTan2.o(.text);
|
||||
*libagbsyscall.a:BgAffineSet.o(.text);
|
||||
*libagbsyscall.a:CpuFastSet.o(.text);
|
||||
*libagbsyscall.a:CpuSet.o(.text);
|
||||
*libagbsyscall.a:Div.o(.text);
|
||||
*libagbsyscall.a:Mod.o(.text);
|
||||
*libagbsyscall.a:LZ77UnCompVram.o(.text);
|
||||
*libagbsyscall.a:LZ77UnCompWram.o(.text);
|
||||
*libagbsyscall.a:MultiBoot.o(.text);
|
||||
*libagbsyscall.a:ObjAffineSet.o(.text);
|
||||
*libagbsyscall.a:RLUnCompVram.o(.text);
|
||||
*libagbsyscall.a:RLUnCompWram.o(.text);
|
||||
*libagbsyscall.a:RegisterRamReset.o(.text);
|
||||
*libagbsyscall.a:SoftReset.o(.text);
|
||||
*libagbsyscall.a:Sqrt.o(.text);
|
||||
*libagbsyscall.a:VBlankIntrWait.o(.text);
|
||||
*libsiirtc.a:siirtc.o(.text);
|
||||
src/agb_flash.o(.text);
|
||||
src/agb_flash_1m.o(.text);
|
||||
src/agb_flash_mx.o(.text);
|
||||
asm/libagbsyscall.o(.text);
|
||||
src/siirtc.o(.text);
|
||||
*libgcc.a:_call_via_rX.o(.text);
|
||||
*libgcc.a:_modsi3.o(.text);
|
||||
*libgcc.a:_umodsi3.o(.text);
|
||||
@@ -52,11 +37,11 @@ SECTIONS {
|
||||
lib_rodata :
|
||||
ALIGN(4)
|
||||
{
|
||||
*libagb_flash.a:agb_flash.o(.rodata);
|
||||
*libagb_flash.a:agb_flash_1m.o(.rodata);
|
||||
*libagb_flash.a:agb_flash_mx.o(.rodata);
|
||||
*libagb_flash.a:agb_flash_le.o(.rodata);
|
||||
*libsiirtc.a:siirtc.o(.rodata);
|
||||
src/agb_flash.o(.rodata);
|
||||
src/agb_flash_1m.o(.rodata);
|
||||
src/agb_flash_mx.o(.rodata);
|
||||
src/agb_flash_le.o(.rodata);
|
||||
src/siirtc.o(.rodata);
|
||||
}
|
||||
|
||||
. = 0x2020000;
|
||||
|
||||
@@ -0,0 +1,296 @@
|
||||
#include <gba/gba.h>
|
||||
#include <gba/flash_internal.h>
|
||||
|
||||
static u8 sTimerNum;
|
||||
static u16 sTimerCount;
|
||||
static vu16 *sTimerReg;
|
||||
static u16 sSavedIme;
|
||||
|
||||
u8 gFlashTimeoutFlag;
|
||||
u8 (*PollFlashStatus)(u8 *);
|
||||
const struct FlashType *gFlash;
|
||||
u16 gFlashNumRemainingBytes;
|
||||
const u16 *gFlashMaxTime;
|
||||
|
||||
u16 (*ProgramFlashByte)(u16, u32, u8);
|
||||
u16 (*ProgramFlashSector)(u16, void *);
|
||||
u16 (*EraseFlashChip)(void);
|
||||
u16 (*EraseFlashSector)(u16);
|
||||
u16 (*WaitForFlashWrite)(u8, u8 *, u8);
|
||||
|
||||
void SetReadFlash1(u16 *dest);
|
||||
|
||||
void SwitchFlashBank(u8 bankNum)
|
||||
{
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
FLASH_WRITE(0x5555, 0xB0);
|
||||
FLASH_WRITE(0x0000, bankNum);
|
||||
}
|
||||
|
||||
#define DELAY() \
|
||||
do { \
|
||||
vu16 i; \
|
||||
for (i = 20000; i != 0; i--) \
|
||||
; \
|
||||
} while (0)
|
||||
|
||||
u16 ReadFlashId(void)
|
||||
{
|
||||
u16 flashId;
|
||||
u16 readFlash1Buffer[0x20];
|
||||
u8 (*readFlash1)(u8 *);
|
||||
|
||||
SetReadFlash1(readFlash1Buffer);
|
||||
readFlash1 = (u8 (*)(u8 *))((s32)readFlash1Buffer + 1);
|
||||
|
||||
// Enter ID mode.
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
FLASH_WRITE(0x5555, 0x90);
|
||||
DELAY();
|
||||
|
||||
flashId = readFlash1(FLASH_BASE + 1) << 8;
|
||||
flashId |= readFlash1(FLASH_BASE);
|
||||
|
||||
// Leave ID mode.
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
FLASH_WRITE(0x5555, 0xF0);
|
||||
FLASH_WRITE(0x5555, 0xF0);
|
||||
DELAY();
|
||||
|
||||
return flashId;
|
||||
}
|
||||
|
||||
void FlashTimerIntr(void)
|
||||
{
|
||||
if (sTimerCount != 0 && --sTimerCount == 0)
|
||||
gFlashTimeoutFlag = 1;
|
||||
}
|
||||
|
||||
u16 SetFlashTimerIntr(u8 timerNum, void (**intrFunc)(void))
|
||||
{
|
||||
if (timerNum >= 4)
|
||||
return 1;
|
||||
|
||||
sTimerNum = timerNum;
|
||||
sTimerReg = ®_TMCNT(sTimerNum);
|
||||
*intrFunc = FlashTimerIntr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void StartFlashTimer(u8 phase)
|
||||
{
|
||||
const u16 *maxTime = &gFlashMaxTime[phase * 3];
|
||||
sSavedIme = REG_IME;
|
||||
REG_IME = 0;
|
||||
sTimerReg[1] = 0;
|
||||
REG_IE |= (INTR_FLAG_TIMER0 << sTimerNum);
|
||||
gFlashTimeoutFlag = 0;
|
||||
sTimerCount = *maxTime++;
|
||||
*sTimerReg++ = *maxTime++;
|
||||
*sTimerReg-- = *maxTime++;
|
||||
REG_IF = (INTR_FLAG_TIMER0 << sTimerNum);
|
||||
REG_IME = 1;
|
||||
}
|
||||
|
||||
void StopFlashTimer(void)
|
||||
{
|
||||
REG_IME = 0;
|
||||
*sTimerReg++ = 0;
|
||||
*sTimerReg-- = 0;
|
||||
REG_IE &= ~(INTR_FLAG_TIMER0 << sTimerNum);
|
||||
REG_IME = sSavedIme;
|
||||
}
|
||||
|
||||
u8 ReadFlash1(u8 *addr)
|
||||
{
|
||||
return *addr;
|
||||
}
|
||||
|
||||
void SetReadFlash1(u16 *dest)
|
||||
{
|
||||
u16 *src;
|
||||
u16 i;
|
||||
|
||||
PollFlashStatus = (u8 (*)(u8 *))((s32)dest + 1);
|
||||
|
||||
src = (u16 *)ReadFlash1;
|
||||
src = (u16 *)((s32)src ^ 1);
|
||||
|
||||
i = ((s32)SetReadFlash1 - (s32)ReadFlash1) >> 1;
|
||||
|
||||
while (i != 0)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
i--;
|
||||
}
|
||||
}
|
||||
|
||||
void ReadFlash_Core(u8 *src, u8 *dest, u32 size)
|
||||
{
|
||||
while (size-- != 0)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
}
|
||||
|
||||
void ReadFlash(u16 sectorNum, u32 offset, void *dest, u32 size)
|
||||
{
|
||||
u8 *src;
|
||||
u16 i;
|
||||
u16 readFlash_Core_Buffer[0x40];
|
||||
u16 *funcSrc;
|
||||
u16 *funcDest;
|
||||
void (*readFlash_Core)(u8 *, u8 *, u32);
|
||||
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
|
||||
|
||||
if (gFlash->romSize == FLASH_ROM_SIZE_1M)
|
||||
{
|
||||
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
|
||||
sectorNum %= SECTORS_PER_BANK;
|
||||
}
|
||||
|
||||
funcSrc = (u16 *)ReadFlash_Core;
|
||||
funcSrc = (u16 *)((s32)funcSrc ^ 1);
|
||||
funcDest = readFlash_Core_Buffer;
|
||||
|
||||
i = ((s32)ReadFlash - (s32)ReadFlash_Core) >> 1;
|
||||
|
||||
while (i != 0)
|
||||
{
|
||||
*funcDest++ = *funcSrc++;
|
||||
i--;
|
||||
}
|
||||
|
||||
readFlash_Core = (void (*)(u8 *, u8 *, u32))((s32)readFlash_Core_Buffer + 1);
|
||||
|
||||
src = FLASH_BASE + (sectorNum << gFlash->sector.shift) + offset;
|
||||
|
||||
readFlash_Core(src, dest, size);
|
||||
}
|
||||
|
||||
u32 VerifyFlashSector_Core(u8 *src, u8 *tgt, u32 size)
|
||||
{
|
||||
while (size-- != 0)
|
||||
{
|
||||
if (*tgt++ != *src++)
|
||||
return (u32)(tgt - 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 VerifyFlashSector(u16 sectorNum, u8 *src)
|
||||
{
|
||||
u16 i;
|
||||
u16 verifyFlashSector_Core_Buffer[0x80];
|
||||
u16 *funcSrc;
|
||||
u16 *funcDest;
|
||||
u8 *tgt;
|
||||
u16 size;
|
||||
u32 (*verifyFlashSector_Core)(u8 *, u8 *, u32);
|
||||
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
|
||||
|
||||
if (gFlash->romSize == FLASH_ROM_SIZE_1M)
|
||||
{
|
||||
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
|
||||
sectorNum %= SECTORS_PER_BANK;
|
||||
}
|
||||
|
||||
funcSrc = (u16 *)VerifyFlashSector_Core;
|
||||
funcSrc = (u16 *)((s32)funcSrc ^ 1);
|
||||
funcDest = verifyFlashSector_Core_Buffer;
|
||||
|
||||
i = ((s32)VerifyFlashSector - (s32)VerifyFlashSector_Core) >> 1;
|
||||
|
||||
while (i != 0)
|
||||
{
|
||||
*funcDest++ = *funcSrc++;
|
||||
i--;
|
||||
}
|
||||
|
||||
verifyFlashSector_Core = (u32 (*)(u8 *, u8 *, u32))((s32)verifyFlashSector_Core_Buffer + 1);
|
||||
|
||||
tgt = FLASH_BASE + (sectorNum << gFlash->sector.shift);
|
||||
size = gFlash->sector.size;
|
||||
|
||||
return verifyFlashSector_Core(src, tgt, size);
|
||||
}
|
||||
|
||||
u32 VerifyFlashSectorNBytes(u16 sectorNum, u8 *src, u32 n)
|
||||
{
|
||||
u16 i;
|
||||
u16 verifyFlashSector_Core_Buffer[0x80];
|
||||
u16 *funcSrc;
|
||||
u16 *funcDest;
|
||||
u8 *tgt;
|
||||
u32 (*verifyFlashSector_Core)(u8 *, u8 *, u32);
|
||||
|
||||
if (gFlash->romSize == FLASH_ROM_SIZE_1M)
|
||||
{
|
||||
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
|
||||
sectorNum %= SECTORS_PER_BANK;
|
||||
}
|
||||
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
|
||||
|
||||
funcSrc = (u16 *)VerifyFlashSector_Core;
|
||||
funcSrc = (u16 *)((s32)funcSrc ^ 1);
|
||||
funcDest = verifyFlashSector_Core_Buffer;
|
||||
|
||||
i = ((s32)VerifyFlashSector - (s32)VerifyFlashSector_Core) >> 1;
|
||||
|
||||
while (i != 0)
|
||||
{
|
||||
*funcDest++ = *funcSrc++;
|
||||
i--;
|
||||
}
|
||||
|
||||
verifyFlashSector_Core = (u32 (*)(u8 *, u8 *, u32))((s32)verifyFlashSector_Core_Buffer + 1);
|
||||
|
||||
tgt = FLASH_BASE + (sectorNum << gFlash->sector.shift);
|
||||
|
||||
return verifyFlashSector_Core(src, tgt, n);
|
||||
}
|
||||
|
||||
u32 ProgramFlashSectorAndVerify(u16 sectorNum, u8 *src)
|
||||
{
|
||||
u8 i;
|
||||
u32 result;
|
||||
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
result = ProgramFlashSector(sectorNum, src);
|
||||
if (result != 0)
|
||||
continue;
|
||||
|
||||
result = VerifyFlashSector(sectorNum, src);
|
||||
if (result == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
u32 ProgramFlashSectorAndVerifyNBytes(u16 sectorNum, void *src, u32 n)
|
||||
{
|
||||
u8 i;
|
||||
u32 result;
|
||||
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
result = ProgramFlashSector(sectorNum, src);
|
||||
if (result != 0)
|
||||
continue;
|
||||
|
||||
result = VerifyFlashSectorNBytes(sectorNum, src, n);
|
||||
if (result == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
@@ -0,0 +1,86 @@
|
||||
#include "gba/gba.h"
|
||||
#include "gba/flash_internal.h"
|
||||
|
||||
static const char AgbLibFlashVersion[] = "FLASH1M_V103";
|
||||
|
||||
const struct FlashSetupInfo * const sSetupInfos[] =
|
||||
{
|
||||
&MX29L010,
|
||||
&LE26FV10N1TS,
|
||||
&DefaultFlash
|
||||
};
|
||||
|
||||
u32 IdentifyFlash(void)
|
||||
{
|
||||
u16 result;
|
||||
u16 flashId;
|
||||
const struct FlashSetupInfo * const *setupInfo;
|
||||
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
|
||||
|
||||
flashId = ReadFlashId();
|
||||
|
||||
setupInfo = sSetupInfos;
|
||||
result = 1;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
if ((*setupInfo)->type.ids.separate.makerId == 0)
|
||||
break;
|
||||
|
||||
if (flashId == (*setupInfo)->type.ids.joined)
|
||||
{
|
||||
result = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
setupInfo++;
|
||||
}
|
||||
|
||||
ProgramFlashByte = (*setupInfo)->programFlashByte;
|
||||
ProgramFlashSector = (*setupInfo)->programFlashSector;
|
||||
EraseFlashChip = (*setupInfo)->eraseFlashChip;
|
||||
EraseFlashSector = (*setupInfo)->eraseFlashSector;
|
||||
WaitForFlashWrite = (*setupInfo)->WaitForFlashWrite;
|
||||
gFlashMaxTime = (*setupInfo)->maxTime;
|
||||
gFlash = &(*setupInfo)->type;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
u16 WaitForFlashWrite_Common(u8 phase, u8 *addr, u8 lastData)
|
||||
{
|
||||
u16 result = 0;
|
||||
u8 status;
|
||||
|
||||
StartFlashTimer(phase);
|
||||
|
||||
while ((status = PollFlashStatus(addr)) != lastData)
|
||||
{
|
||||
if (status & 0x20)
|
||||
{
|
||||
// The write operation exceeded the flash chip's time limit.
|
||||
|
||||
if (PollFlashStatus(addr) == lastData)
|
||||
break;
|
||||
|
||||
FLASH_WRITE(0x5555, 0xF0);
|
||||
result = phase | 0xA000u;
|
||||
break;
|
||||
}
|
||||
|
||||
if (gFlashTimeoutFlag)
|
||||
{
|
||||
if (PollFlashStatus(addr) == lastData)
|
||||
break;
|
||||
|
||||
FLASH_WRITE(0x5555, 0xF0);
|
||||
result = phase | 0xC000u;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
StopFlashTimer();
|
||||
|
||||
return result;
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
#include "gba/gba.h"
|
||||
#include "gba/flash_internal.h"
|
||||
|
||||
const u16 leMaxTime[] =
|
||||
{
|
||||
10, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
|
||||
10, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
|
||||
2000, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
|
||||
2000, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
|
||||
};
|
||||
|
||||
const struct FlashSetupInfo LE26FV10N1TS =
|
||||
{
|
||||
ProgramFlashByte_MX,
|
||||
ProgramFlashSector_MX,
|
||||
EraseFlashChip_MX,
|
||||
EraseFlashSector_MX,
|
||||
WaitForFlashWrite_Common,
|
||||
leMaxTime,
|
||||
{
|
||||
131072, // ROM size
|
||||
{
|
||||
4096, // sector size
|
||||
12, // bit shift to multiply by sector size (4096 == 1 << 12)
|
||||
32, // number of sectors
|
||||
0 // appears to be unused
|
||||
},
|
||||
{ 3, 1 }, // wait state setup data
|
||||
{ { 0x62, 0x13 } } // ID
|
||||
}
|
||||
};
|
||||
@@ -0,0 +1,193 @@
|
||||
#include "gba/gba.h"
|
||||
#include "gba/flash_internal.h"
|
||||
|
||||
const u16 mxMaxTime[] =
|
||||
{
|
||||
10, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
|
||||
10, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
|
||||
2000, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
|
||||
2000, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
|
||||
};
|
||||
|
||||
const struct FlashSetupInfo MX29L010 =
|
||||
{
|
||||
ProgramFlashByte_MX,
|
||||
ProgramFlashSector_MX,
|
||||
EraseFlashChip_MX,
|
||||
EraseFlashSector_MX,
|
||||
WaitForFlashWrite_Common,
|
||||
mxMaxTime,
|
||||
{
|
||||
131072, // ROM size
|
||||
{
|
||||
4096, // sector size
|
||||
12, // bit shift to multiply by sector size (4096 == 1 << 12)
|
||||
32, // number of sectors
|
||||
0 // appears to be unused
|
||||
},
|
||||
{ 3, 1 }, // wait state setup data
|
||||
{ { 0xC2, 0x09 } } // ID
|
||||
}
|
||||
};
|
||||
|
||||
const struct FlashSetupInfo DefaultFlash =
|
||||
{
|
||||
ProgramFlashByte_MX,
|
||||
ProgramFlashSector_MX,
|
||||
EraseFlashChip_MX,
|
||||
EraseFlashSector_MX,
|
||||
WaitForFlashWrite_Common,
|
||||
mxMaxTime,
|
||||
{
|
||||
131072, // ROM size
|
||||
{
|
||||
4096, // sector size
|
||||
12, // bit shift to multiply by sector size (4096 == 1 << 12)
|
||||
32, // number of sectors
|
||||
0 // appears to be unused
|
||||
},
|
||||
{ 3, 1 }, // wait state setup data
|
||||
{ { 0x00, 0x00 } } // ID of 0
|
||||
}
|
||||
};
|
||||
|
||||
u16 EraseFlashChip_MX(void)
|
||||
{
|
||||
u16 result;
|
||||
u16 readFlash1Buffer[0x20];
|
||||
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | gFlash->wait[0];
|
||||
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
FLASH_WRITE(0x5555, 0x80);
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
FLASH_WRITE(0x5555, 0x10);
|
||||
|
||||
SetReadFlash1(readFlash1Buffer);
|
||||
|
||||
result = WaitForFlashWrite(3, FLASH_BASE, 0xFF);
|
||||
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
u16 EraseFlashSector_MX(u16 sectorNum)
|
||||
{
|
||||
u16 numTries;
|
||||
u16 result;
|
||||
u8 *addr;
|
||||
u16 readFlash1Buffer[0x20];
|
||||
|
||||
if (sectorNum >= gFlash->sector.count)
|
||||
return 0x80FF;
|
||||
|
||||
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
|
||||
sectorNum %= SECTORS_PER_BANK;
|
||||
|
||||
numTries = 0;
|
||||
|
||||
try_erase:
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | gFlash->wait[0];
|
||||
|
||||
addr = FLASH_BASE + (sectorNum << gFlash->sector.shift);
|
||||
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
FLASH_WRITE(0x5555, 0x80);
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
*addr = 0x30;
|
||||
|
||||
SetReadFlash1(readFlash1Buffer);
|
||||
|
||||
result = WaitForFlashWrite(2, addr, 0xFF);
|
||||
|
||||
if (!(result & 0xA000) || numTries > 3)
|
||||
goto done;
|
||||
|
||||
numTries++;
|
||||
|
||||
goto try_erase;
|
||||
|
||||
done:
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
u16 ProgramFlashByte_MX(u16 sectorNum, u32 offset, u8 data)
|
||||
{
|
||||
u8 *addr;
|
||||
u16 readFlash1Buffer[0x20];
|
||||
|
||||
if (offset >= gFlash->sector.size)
|
||||
return 0x8000;
|
||||
|
||||
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
|
||||
sectorNum %= SECTORS_PER_BANK;
|
||||
|
||||
addr = FLASH_BASE + (sectorNum << gFlash->sector.shift) + offset;
|
||||
|
||||
SetReadFlash1(readFlash1Buffer);
|
||||
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | gFlash->wait[0];
|
||||
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
FLASH_WRITE(0x5555, 0xA0);
|
||||
*addr = data;
|
||||
|
||||
return WaitForFlashWrite(1, addr, data);
|
||||
}
|
||||
|
||||
static u16 ProgramByte(u8 *src, u8 *dest)
|
||||
{
|
||||
FLASH_WRITE(0x5555, 0xAA);
|
||||
FLASH_WRITE(0x2AAA, 0x55);
|
||||
FLASH_WRITE(0x5555, 0xA0);
|
||||
*dest = *src;
|
||||
|
||||
return WaitForFlashWrite(1, dest, *src);
|
||||
}
|
||||
|
||||
u16 ProgramFlashSector_MX(u16 sectorNum, void *src)
|
||||
{
|
||||
u16 result;
|
||||
u8 *dest;
|
||||
u16 readFlash1Buffer[0x20];
|
||||
|
||||
if (sectorNum >= gFlash->sector.count)
|
||||
return 0x80FF;
|
||||
|
||||
result = EraseFlashSector_MX(sectorNum);
|
||||
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
|
||||
sectorNum %= SECTORS_PER_BANK;
|
||||
|
||||
SetReadFlash1(readFlash1Buffer);
|
||||
|
||||
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | gFlash->wait[0];
|
||||
|
||||
gFlashNumRemainingBytes = gFlash->sector.size;
|
||||
dest = FLASH_BASE + (sectorNum << gFlash->sector.shift);
|
||||
|
||||
while (gFlashNumRemainingBytes > 0)
|
||||
{
|
||||
result = ProgramByte(src, dest);
|
||||
|
||||
if (result != 0)
|
||||
break;
|
||||
|
||||
gFlashNumRemainingBytes--;
|
||||
src++;
|
||||
dest++;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
@@ -1,5 +1,5 @@
|
||||
#include <gba/gba.h>
|
||||
#include <agb_flash.h>
|
||||
#include "gba/gba.h"
|
||||
#include "gba/flash_internal.h"
|
||||
#include "constants/vars.h"
|
||||
#include "global.h"
|
||||
#include "main.h"
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
#include <gba/gba.h>
|
||||
#include "gba/gba.h"
|
||||
#include "global.h"
|
||||
#include "main.h"
|
||||
#include "rtc.h"
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#include <gba/gba.h>
|
||||
#include <siirtc.h>
|
||||
#include "gba/gba.h"
|
||||
#include "siirtc.h"
|
||||
#include "global.h"
|
||||
#include "main.h"
|
||||
|
||||
|
||||
@@ -0,0 +1,432 @@
|
||||
// Ruby/Sapphire/Emerald cartridges contain a Seiko Instruments Inc. (SII)
|
||||
// S-3511A real-time clock (RTC). This library ("SIIRTC_V001") is for
|
||||
// communicating with the RTC.
|
||||
|
||||
#include "gba/gba.h"
|
||||
#include "siirtc.h"
|
||||
|
||||
#define STATUS_INTFE 0x02 // frequency interrupt enable
|
||||
#define STATUS_INTME 0x08 // per-minute interrupt enable
|
||||
#define STATUS_INTAE 0x20 // alarm interrupt enable
|
||||
#define STATUS_24HOUR 0x40 // 0: 12-hour mode, 1: 24-hour mode
|
||||
#define STATUS_POWER 0x80 // power on or power failure occurred
|
||||
|
||||
#define TEST_MODE 0x80 // flag in the "second" byte
|
||||
|
||||
#define ALARM_AM 0x00
|
||||
#define ALARM_PM 0x80
|
||||
|
||||
#define OFFSET_YEAR offsetof(struct SiiRtcInfo, year)
|
||||
#define OFFSET_MONTH offsetof(struct SiiRtcInfo, month)
|
||||
#define OFFSET_DAY offsetof(struct SiiRtcInfo, day)
|
||||
#define OFFSET_DAY_OF_WEEK offsetof(struct SiiRtcInfo, dayOfWeek)
|
||||
#define OFFSET_HOUR offsetof(struct SiiRtcInfo, hour)
|
||||
#define OFFSET_MINUTE offsetof(struct SiiRtcInfo, minute)
|
||||
#define OFFSET_SECOND offsetof(struct SiiRtcInfo, second)
|
||||
#define OFFSET_STATUS offsetof(struct SiiRtcInfo, status)
|
||||
#define OFFSET_ALARM_HOUR offsetof(struct SiiRtcInfo, alarmHour)
|
||||
#define OFFSET_ALARM_MINUTE offsetof(struct SiiRtcInfo, alarmMinute)
|
||||
|
||||
#define INFO_BUF(info, index) (*((u8 *)(info) + (index)))
|
||||
|
||||
#define DATETIME_BUF(info, index) INFO_BUF(info, OFFSET_YEAR + index)
|
||||
#define DATETIME_BUF_LEN (OFFSET_SECOND - OFFSET_YEAR + 1)
|
||||
|
||||
#define TIME_BUF(info, index) INFO_BUF(info, OFFSET_HOUR + index)
|
||||
#define TIME_BUF_LEN (OFFSET_SECOND - OFFSET_HOUR + 1)
|
||||
|
||||
#define WR 0 // command for writing data
|
||||
#define RD 1 // command for reading data
|
||||
|
||||
#define CMD(n) (0x60 | (n << 1))
|
||||
|
||||
#define CMD_RESET CMD(0)
|
||||
#define CMD_STATUS CMD(1)
|
||||
#define CMD_DATETIME CMD(2)
|
||||
#define CMD_TIME CMD(3)
|
||||
#define CMD_ALARM CMD(4)
|
||||
|
||||
#define GPIO_PORT_DATA (*(vu16 *)0x80000C4)
|
||||
#define GPIO_PORT_DIRECTION (*(vu16 *)0x80000C6)
|
||||
#define GPIO_PORT_READ_ENABLE (*(vu16 *)0x80000C8)
|
||||
|
||||
extern vu16 GPIOPortDirection;
|
||||
|
||||
static u16 sDummy; // unused variable
|
||||
static bool8 sLocked;
|
||||
|
||||
static int WriteCommand(u8 value);
|
||||
static int WriteData(u8 value);
|
||||
static u8 ReadData();
|
||||
static void EnableGpioPortRead();
|
||||
static void DisableGpioPortRead();
|
||||
|
||||
static const char AgbLibRtcVersion[] = "SIIRTC_V001";
|
||||
|
||||
void SiiRtcUnprotect()
|
||||
{
|
||||
EnableGpioPortRead();
|
||||
sLocked = FALSE;
|
||||
}
|
||||
|
||||
void SiiRtcProtect()
|
||||
{
|
||||
DisableGpioPortRead();
|
||||
sLocked = TRUE;
|
||||
}
|
||||
|
||||
u8 SiiRtcProbe()
|
||||
{
|
||||
u8 errorCode;
|
||||
struct SiiRtcInfo rtc;
|
||||
|
||||
if (!SiiRtcGetStatus(&rtc))
|
||||
return 0;
|
||||
|
||||
errorCode = 0;
|
||||
|
||||
if ((rtc.status & (SIIRTCINFO_POWER | SIIRTCINFO_24HOUR)) == SIIRTCINFO_POWER
|
||||
|| (rtc.status & (SIIRTCINFO_POWER | SIIRTCINFO_24HOUR)) == 0)
|
||||
{
|
||||
// The RTC is in 12-hour mode. Reset it and switch to 24-hour mode.
|
||||
|
||||
// Note that the conditions are redundant and equivalent to simply
|
||||
// "(rtc.status & SIIRTCINFO_24HOUR) == 0". It's possible that this
|
||||
// was also intended to handle resetting the clock after power failure
|
||||
// but a mistake was made.
|
||||
|
||||
if (!SiiRtcReset())
|
||||
return 0;
|
||||
|
||||
errorCode++;
|
||||
}
|
||||
|
||||
SiiRtcGetTime(&rtc);
|
||||
|
||||
if (rtc.second & TEST_MODE)
|
||||
{
|
||||
// The RTC is in test mode. Reset it to leave test mode.
|
||||
|
||||
if (!SiiRtcReset())
|
||||
return (errorCode << 4) & 0xF0;
|
||||
|
||||
errorCode++;
|
||||
}
|
||||
|
||||
return (errorCode << 4) | 1;
|
||||
}
|
||||
|
||||
bool8 SiiRtcReset()
|
||||
{
|
||||
u8 result;
|
||||
struct SiiRtcInfo rtc;
|
||||
|
||||
if (sLocked == TRUE)
|
||||
return FALSE;
|
||||
|
||||
sLocked = TRUE;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
GPIO_PORT_DIRECTION = 7;
|
||||
|
||||
WriteCommand(CMD_RESET | WR);
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 1;
|
||||
|
||||
sLocked = FALSE;
|
||||
|
||||
rtc.status = SIIRTCINFO_24HOUR;
|
||||
|
||||
result = SiiRtcSetStatus(&rtc);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
bool8 SiiRtcGetStatus(struct SiiRtcInfo *rtc)
|
||||
{
|
||||
u8 statusData;
|
||||
|
||||
if (sLocked == TRUE)
|
||||
return FALSE;
|
||||
|
||||
sLocked = TRUE;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
GPIO_PORT_DIRECTION = 7;
|
||||
|
||||
WriteCommand(CMD_STATUS | RD);
|
||||
|
||||
GPIO_PORT_DIRECTION = 5;
|
||||
|
||||
statusData = ReadData();
|
||||
|
||||
rtc->status = (statusData & (STATUS_POWER | STATUS_24HOUR))
|
||||
| ((statusData & STATUS_INTAE) >> 3)
|
||||
| ((statusData & STATUS_INTME) >> 2)
|
||||
| ((statusData & STATUS_INTFE) >> 1);
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 1;
|
||||
|
||||
sLocked = FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
bool8 SiiRtcSetStatus(struct SiiRtcInfo *rtc)
|
||||
{
|
||||
u8 statusData;
|
||||
|
||||
if (sLocked == TRUE)
|
||||
return FALSE;
|
||||
|
||||
sLocked = TRUE;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
statusData = STATUS_24HOUR
|
||||
| ((rtc->status & SIIRTCINFO_INTAE) << 3)
|
||||
| ((rtc->status & SIIRTCINFO_INTME) << 2)
|
||||
| ((rtc->status & SIIRTCINFO_INTFE) << 1);
|
||||
|
||||
GPIO_PORT_DIRECTION = 7;
|
||||
|
||||
WriteCommand(CMD_STATUS | WR);
|
||||
|
||||
WriteData(statusData);
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 1;
|
||||
|
||||
sLocked = FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
bool8 SiiRtcGetDateTime(struct SiiRtcInfo *rtc)
|
||||
{
|
||||
u8 i;
|
||||
|
||||
if (sLocked == TRUE)
|
||||
return FALSE;
|
||||
|
||||
sLocked = TRUE;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
GPIO_PORT_DIRECTION = 7;
|
||||
|
||||
WriteCommand(CMD_DATETIME | RD);
|
||||
|
||||
GPIO_PORT_DIRECTION = 5;
|
||||
|
||||
for (i = 0; i < DATETIME_BUF_LEN; i++)
|
||||
DATETIME_BUF(rtc, i) = ReadData();
|
||||
|
||||
INFO_BUF(rtc, OFFSET_HOUR) &= 0x7F;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 1;
|
||||
|
||||
sLocked = FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
bool8 SiiRtcSetDateTime(struct SiiRtcInfo *rtc)
|
||||
{
|
||||
u8 i;
|
||||
|
||||
if (sLocked == TRUE)
|
||||
return FALSE;
|
||||
|
||||
sLocked = TRUE;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
GPIO_PORT_DIRECTION = 7;
|
||||
|
||||
WriteCommand(CMD_DATETIME | WR);
|
||||
|
||||
for (i = 0; i < DATETIME_BUF_LEN; i++)
|
||||
WriteData(DATETIME_BUF(rtc, i));
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 1;
|
||||
|
||||
sLocked = FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
bool8 SiiRtcGetTime(struct SiiRtcInfo *rtc)
|
||||
{
|
||||
u8 i;
|
||||
|
||||
if (sLocked == TRUE)
|
||||
return FALSE;
|
||||
|
||||
sLocked = TRUE;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
GPIO_PORT_DIRECTION = 7;
|
||||
|
||||
WriteCommand(CMD_TIME | RD);
|
||||
|
||||
GPIO_PORT_DIRECTION = 5;
|
||||
|
||||
for (i = 0; i < TIME_BUF_LEN; i++)
|
||||
TIME_BUF(rtc, i) = ReadData();
|
||||
|
||||
INFO_BUF(rtc, OFFSET_HOUR) &= 0x7F;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 1;
|
||||
|
||||
sLocked = FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
bool8 SiiRtcSetTime(struct SiiRtcInfo *rtc)
|
||||
{
|
||||
u8 i;
|
||||
|
||||
if (sLocked == TRUE)
|
||||
return FALSE;
|
||||
|
||||
sLocked = TRUE;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
GPIO_PORT_DIRECTION = 7;
|
||||
|
||||
WriteCommand(CMD_TIME | WR);
|
||||
|
||||
for (i = 0; i < TIME_BUF_LEN; i++)
|
||||
WriteData(TIME_BUF(rtc, i));
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 1;
|
||||
|
||||
sLocked = FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
bool8 SiiRtcSetAlarm(struct SiiRtcInfo *rtc)
|
||||
{
|
||||
u8 i;
|
||||
u8 alarmData[2];
|
||||
|
||||
if (sLocked == TRUE)
|
||||
return FALSE;
|
||||
|
||||
sLocked = TRUE;
|
||||
|
||||
// Decode BCD.
|
||||
alarmData[0] = (rtc->alarmHour & 0xF) + 10 * ((rtc->alarmHour >> 4) & 0xF);
|
||||
|
||||
// The AM/PM flag must be set correctly even in 24-hour mode.
|
||||
|
||||
if (alarmData[0] < 12)
|
||||
alarmData[0] = rtc->alarmHour | ALARM_AM;
|
||||
else
|
||||
alarmData[0] = rtc->alarmHour | ALARM_PM;
|
||||
|
||||
alarmData[1] = rtc->alarmMinute;
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
GPIOPortDirection = 7; // Why is this the only instance that uses a symbol?
|
||||
|
||||
WriteCommand(CMD_ALARM | WR);
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
WriteData(alarmData[i]);
|
||||
|
||||
GPIO_PORT_DATA = 1;
|
||||
GPIO_PORT_DATA = 1;
|
||||
|
||||
sLocked = FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static int WriteCommand(u8 value)
|
||||
{
|
||||
u8 i;
|
||||
u8 temp;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
temp = ((value >> (7 - i)) & 1);
|
||||
GPIO_PORT_DATA = (temp << 1) | 4;
|
||||
GPIO_PORT_DATA = (temp << 1) | 4;
|
||||
GPIO_PORT_DATA = (temp << 1) | 4;
|
||||
GPIO_PORT_DATA = (temp << 1) | 5;
|
||||
}
|
||||
|
||||
// control reaches end of non-void function
|
||||
}
|
||||
|
||||
static int WriteData(u8 value)
|
||||
{
|
||||
u8 i;
|
||||
u8 temp;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
temp = ((value >> i) & 1);
|
||||
GPIO_PORT_DATA = (temp << 1) | 4;
|
||||
GPIO_PORT_DATA = (temp << 1) | 4;
|
||||
GPIO_PORT_DATA = (temp << 1) | 4;
|
||||
GPIO_PORT_DATA = (temp << 1) | 5;
|
||||
}
|
||||
|
||||
// control reaches end of non-void function
|
||||
}
|
||||
|
||||
static u8 ReadData()
|
||||
{
|
||||
u8 i;
|
||||
u8 temp;
|
||||
u8 value;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
GPIO_PORT_DATA = 4;
|
||||
GPIO_PORT_DATA = 4;
|
||||
GPIO_PORT_DATA = 4;
|
||||
GPIO_PORT_DATA = 4;
|
||||
GPIO_PORT_DATA = 4;
|
||||
GPIO_PORT_DATA = 5;
|
||||
|
||||
temp = ((GPIO_PORT_DATA & 2) >> 1);
|
||||
value = (value >> 1) | (temp << 7); // UB: accessing uninitialized var
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static void EnableGpioPortRead()
|
||||
{
|
||||
GPIO_PORT_READ_ENABLE = 1;
|
||||
}
|
||||
|
||||
static void DisableGpioPortRead()
|
||||
{
|
||||
GPIO_PORT_READ_ENABLE = 0;
|
||||
}
|
||||
@@ -1,5 +1,5 @@
|
||||
.include "src/main.o"
|
||||
.include "src/rtc.o"
|
||||
.include "src/flash.o"
|
||||
.include "*libagb_flash.a:agb_flash.o"
|
||||
.include "*libsiirtc.a:siirtc.o"
|
||||
.include "src/agb_flash.o"
|
||||
.include "src/siirtc.o"
|
||||
|
||||
@@ -26,4 +26,4 @@ gCurSaveChunk:
|
||||
gFlashIdentIsValid: @ 0x0300123C
|
||||
.space 0x4
|
||||
|
||||
.include "*libagb_flash.a:agb_flash.o"
|
||||
.include "agb_flash.o"
|
||||
|
||||
Reference in New Issue
Block a user