Decompile librfu_intr against agbcc_arm
This commit is contained in:
PikalaxALT
@@ -173,6 +173,9 @@ $(C_BUILDDIR)/isagbprn.o: CFLAGS := -mthumb-interwork
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$(C_BUILDDIR)/trainer_tower.o: CFLAGS += -ffreestanding
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$(C_BUILDDIR)/flying.o: CFLAGS += -ffreestanding
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$(C_BUILDDIR)/librfu_intr.o: CC1 := tools/agbcc/bin/agbcc_arm
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$(C_BUILDDIR)/librfu_intr.o: CFLAGS := -O2 -mthumb-interwork -quiet
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ifeq ($(NODEP),1)
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$(C_BUILDDIR)/%.o: c_dep :=
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else
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@@ -4,694 +4,3 @@
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.syntax unified
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.text
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arm_func_start IntrSIO32
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IntrSIO32: @ 81DFC50
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mov r12, sp
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stmdb sp!, {r11,r12,lr,pc}
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ldr r3, _081DFCB0 @ =gSTWIStatus
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ldr r0, [r3]
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ldr r2, [r0]
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sub r11, r12, 0x4
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cmp r2, 0xA
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bne _081DFC8C
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ldr r0, [r0, 0x20]
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cmp r0, 0
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ldmdbeq r11, {r11,sp,lr}
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bxeq lr
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bl Callback_Dummy_ID
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ldmdb r11, {r11,sp,lr}
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bx lr
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_081DFC8C:
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ldrb r3, [r0, 0x14]
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cmp r3, 0x1
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bne _081DFCA4
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bl sio32intr_clock_master
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ldmdb r11, {r11,sp,lr}
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bx lr
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_081DFCA4:
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bl sio32intr_clock_slave
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ldmdb r11, {r11,sp,lr}
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bx lr
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.align 2, 0
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_081DFCB0: .4byte gSTWIStatus
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arm_func_end IntrSIO32
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arm_func_start sio32intr_clock_master
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sio32intr_clock_master: @ 81DFCB4
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mov r12, sp
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stmdb sp!, {r4-r6,r11,r12,lr,pc}
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mov r0, 0x50
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sub r11, r12, 0x4
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bl STWI_set_timer_in_RAM
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mov r4, 0x120
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ldr r2, _081DFF28 @ =gSTWIStatus
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add r4, r4, 0x4000000
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ldr lr, [r4]
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ldr r12, [r2]
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ldr r3, [r12]
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mov r6, r2
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cmp r3, 0
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bne _081DFD34
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cmp lr, 0x80000000
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bne _081DFDB4
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ldrb r2, [r12, 0x5]
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ldrb r3, [r12, 0x4]
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cmp r2, r3
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bhi _081DFD24
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ldr r3, [r12, 0x24]
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mov r1, r2
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ldr r2, [r3, r1, lsl 2]
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str r2, [r4]
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ldrb r3, [r12, 0x5]
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add r3, r3, 0x1
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strb r3, [r12, 0x5]
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b _081DFE10
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_081DFD24:
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mov r3, 0x1
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str r3, [r12]
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str lr, [r4]
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b _081DFE10
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_081DFD34:
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ldr r3, [r12]
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cmp r3, 0x1
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bne _081DFDC4
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mov r3, 0x99000000
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add r3, r3, 0x660000
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mov r5, 0x80000000
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and r2, lr, r5, asr 15
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cmp r2, r3
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bne _081DFDB4
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mov r3, 0
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strb r3, [r12, 0x8]
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ldr r1, [r6]
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ldrb r0, [r1, 0x8]
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ldr r2, [r1, 0x28]
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str lr, [r2, r0, lsl 2]
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ldrb r3, [r1, 0x8]
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add r3, r3, 0x1
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strb r3, [r1, 0x8]
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ldr r2, [r6]
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strb lr, [r2, 0x9]
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ldr r3, [r6]
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mov r2, lr, lsr 8
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strb r2, [r3, 0x7]
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ldr r1, [r6]
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ldrb r2, [r1, 0x7]
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ldrb r3, [r1, 0x8]
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cmp r2, r3
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bcc _081DFDFC
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mov r3, 0x2
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str r3, [r1]
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str r5, [r4]
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b _081DFE10
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_081DFDB4:
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bl STWI_stop_timer_in_RAM
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mov r0, 0x82
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bl STWI_set_timer_in_RAM
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b _081DFF3C
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_081DFDC4:
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ldr r3, [r12]
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cmp r3, 0x2
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bne _081DFE10
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ldrb r1, [r12, 0x8]
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ldr r2, [r12, 0x28]
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str lr, [r2, r1, lsl 2]
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ldrb r3, [r12, 0x8]
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add r3, r3, 0x1
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strb r3, [r12, 0x8]
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ldr r1, [r6]
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ldrb r2, [r1, 0x7]
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ldrb r3, [r1, 0x8]
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cmp r2, r3
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bcs _081DFE08
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_081DFDFC:
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mov r3, 0x3
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str r3, [r1]
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b _081DFE10
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_081DFE08:
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mov r3, 0x80000000
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str r3, [r4]
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_081DFE10:
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mov r0, 0x1
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bl handshake_wait
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mov r0, r0, lsl 16
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cmp r0, 0x10000
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beq _081DFF3C
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mov r4, 0x128
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add r4, r4, 0x4000000
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mov r5, 0x5000
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add r3, r5, 0xB
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strh r3, [r4]
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mov r0, 0
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bl handshake_wait
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mov r0, r0, lsl 16
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cmp r0, 0x10000
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beq _081DFF3C
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bl STWI_stop_timer_in_RAM
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ldr r1, [r6]
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ldr r0, [r1]
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cmp r0, 0x3
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bne _081DFF2C
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ldrb r3, [r1, 0x9]
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cmp r3, 0xA5
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cmpne r3, 0xA7
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beq _081DFE84
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and r3, r3, 0xFF
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cmp r3, 0xB5
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beq _081DFE84
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cmp r3, 0xB7
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bne _081DFECC
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_081DFE84:
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mov r1, 0x120
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add r1, r1, 0x4000000
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mov r12, 0x128
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add r12, r12, 0x4000000
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ldr r0, [r6]
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mov r3, 0
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strb r3, [r0, 0x14]
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mov r2, 0x80000000
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str r2, [r1]
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add r3, r3, 0x5000
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add r2, r3, 0x2
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strh r2, [r12]
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add r3, r3, 0x82
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strh r3, [r12]
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ldr r2, [r6]
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mov r3, 0x5
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str r3, [r2]
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b _081DFEFC
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_081DFECC:
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cmp r3, 0xEE
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bne _081DFEEC
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add r3, r5, 0x3
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strh r3, [r4]
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mov r2, 0x4
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str r2, [r1]
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strh r0, [r1, 0x12]
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b _081DFEFC
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_081DFEEC:
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add r3, r5, 0x3
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strh r3, [r4]
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mov r2, 0x4
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str r2, [r1]
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_081DFEFC:
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ldr r2, [r6]
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mov r3, 0
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strb r3, [r2, 0x2C]
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ldr r0, [r6]
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ldr r2, [r0, 0x18]
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cmp r2, r3
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beq _081DFF3C
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ldrh r1, [r0, 0x12]
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ldrb r0, [r0, 0x6]
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bl Callback_Dummy_M
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b _081DFF3C
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.align 2, 0
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_081DFF28: .4byte gSTWIStatus
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_081DFF2C:
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add r3, r5, 0x3
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strh r3, [r4]
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add r2, r5, 0x83
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strh r2, [r4]
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_081DFF3C:
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ldmdb r11, {r4-r6,r11,sp,lr}
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bx lr
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arm_func_end sio32intr_clock_master
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arm_func_start sio32intr_clock_slave
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sio32intr_clock_slave: @ 81DFF44
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mov r12, sp
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stmdb sp!, {r4-r6,r11,r12,lr,pc}
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ldr r4, _081E02F0 @ =gSTWIStatus
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mov r0, 0x64
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ldr r3, [r4]
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mov r6, 0
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strb r6, [r3, 0x10]
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sub r11, r12, 0x4
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bl STWI_set_timer_in_RAM
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mov r0, r6
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bl handshake_wait
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mov r0, r0, lsl 16
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cmp r0, 0x10000
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mov r5, r4
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beq _081E0348
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mov r3, 0x128
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add r3, r3, 0x4000000
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mov r2, 0x5000
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add r2, r2, 0xA
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strh r2, [r3]
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mov lr, 0x120
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ldr r0, [r5]
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add lr, lr, 0x4000000
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ldr r12, [lr]
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ldr r3, [r0]
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cmp r3, 0x5
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bne _081E0074
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ldr r3, [r0, 0x28]
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mov r4, 0x1
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mov r0, 0x99000000
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str r12, [r3]
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add r0, r0, 0x660000
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ldr r2, [r5]
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mov r3, r0, lsr 16
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strb r4, [r2, 0x5]
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cmp r3, r12, lsr 16
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bne _081E01C0
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ldr r3, [r5]
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mov r2, r12, lsr 8
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strb r2, [r3, 0x4]
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ldr r2, [r5]
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strb r12, [r2, 0x6]
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ldr r1, [r5]
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ldrb r3, [r1, 0x4]
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cmp r3, r6
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bne _081E0058
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ldrb r2, [r1, 0x6]
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sub r3, r2, 0x27
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cmp r2, 0x36
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cmpne r3, 0x2
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bhi _081E002C
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add r3, r2, 0x80
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strb r3, [r1, 0x9]
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ldr r2, [r5]
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ldrb r3, [r2, 0x9]
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ldr r1, [r2, 0x24]
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add r3, r3, r0
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b _081E00DC
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_081E002C:
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ldr r2, [r1, 0x24]
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ldr r3, _081E02F4 @ =0x996601ee
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str r3, [r2]
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ldr r2, [r5]
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ldrb r3, [r2, 0x6]
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sub r3, r3, 0x10
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cmp r3, 0x2D
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bhi _081E0114
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ldr r3, [r2, 0x24]
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str r4, [r3, 0x4]
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b _081E0120
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_081E0058:
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mov r3, 0x80000000
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str r3, [lr]
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strb r4, [r1, 0x5]
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ldr r2, [r5]
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add r3, r3, 0x80000006
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str r3, [r2]
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b _081E01D0
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_081E0074:
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ldr r3, [r0]
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cmp r3, 0x6
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bne _081E0174
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ldrb r1, [r0, 0x5]
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ldr r2, [r0, 0x28]
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str r12, [r2, r1, lsl 2]
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ldrb r3, [r0, 0x5]
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add r3, r3, 0x1
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strb r3, [r0, 0x5]
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ldr r1, [r5]
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ldrb r2, [r1, 0x4]
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ldrb r3, [r1, 0x5]
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cmp r2, r3
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bcs _081E0168
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ldrb r2, [r1, 0x6]
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sub r3, r2, 0x28
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cmp r2, 0x36
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cmpne r3, 0x1
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bhi _081E00EC
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add r3, r2, 0x80
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strb r3, [r1, 0x9]
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ldr r2, [r5]
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ldrb r3, [r2, 0x9]
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ldr r1, [r2, 0x24]
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orr r3, r3, 0x99000000
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orr r3, r3, 0x660000
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_081E00DC:
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str r3, [r1]
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ldr r2, [r5]
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strb r6, [r2, 0x7]
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b _081E0138
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_081E00EC:
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ldr r2, [r1, 0x24]
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ldr r3, _081E02F4 @ =0x996601ee
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str r3, [r2]
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ldr r2, [r5]
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ldrb r3, [r2, 0x6]
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sub r3, r3, 0x10
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cmp r3, 0x2D
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ldrls r2, [r2, 0x24]
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movls r3, 0x1
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bls _081E011C
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_081E0114:
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ldr r2, [r2, 0x24]
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mov r3, 0x2
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_081E011C:
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str r3, [r2, 0x4]
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_081E0120:
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ldr r2, [r5]
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mov r3, 0x1
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strb r3, [r2, 0x7]
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ldr r1, [r5]
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add r3, r3, 0x2
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strh r3, [r1, 0x12]
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_081E0138:
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ldr r0, [r5]
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ldr r2, [r0, 0x24]
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mov r3, 0x120
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ldr r1, [r2]
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add r3, r3, 0x4000000
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str r1, [r3]
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mov r2, 0x1
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strb r2, [r0, 0x8]
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ldr r1, [r5]
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mov r3, 0x7
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str r3, [r1]
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b _081E01D0
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_081E0168:
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mov r3, 0x80000000
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str r3, [lr]
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b _081E01D0
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_081E0174:
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ldr r3, [r0]
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cmp r3, 0x7
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bne _081E01D0
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cmp r12, 0x80000000
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bne _081E01C0
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ldrb r2, [r0, 0x7]
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ldrb r3, [r0, 0x8]
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cmp r2, r3
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movcc r3, 0x8
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strcc r3, [r0]
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bcc _081E01D0
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ldrb r1, [r0, 0x8]
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ldr r3, [r0, 0x24]
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ldr r2, [r3, r1, lsl 2]
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str r2, [lr]
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ldrb r3, [r0, 0x8]
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add r3, r3, 0x1
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strb r3, [r0, 0x8]
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b _081E01D0
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_081E01C0:
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bl STWI_stop_timer_in_RAM
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mov r0, 0x64
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bl STWI_set_timer_in_RAM
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b _081E0348
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_081E01D0:
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mov r0, 0x1
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bl handshake_wait
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mov r0, r0, lsl 16
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cmp r0, 0x10000
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beq _081E0348
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mov r6, r5
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ldr r3, [r6]
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ldr r2, [r3]
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cmp r2, 0x8
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bne _081E0298
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mov r4, 0x128
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add r4, r4, 0x4000000
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mov r3, 0x5000
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add r3, r3, 0x2
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strh r3, [r4]
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bl STWI_stop_timer_in_RAM
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ldr r0, [r6]
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ldrh r3, [r0, 0x12]
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cmp r3, 0x3
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bne _081E0244
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bl STWI_init_slave
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ldr r3, [r6]
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ldr r1, [r3, 0x1C]
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cmp r1, 0
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beq _081E0348
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mov r0, 0x1EC
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add r0, r0, 0x2
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bl Callback_Dummy_S
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b _081E0348
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_081E0244:
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mov r3, 0x120
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add r3, r3, 0x4000000
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mov r1, 0
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str r1, [r3]
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mov r2, 0x5000
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strh r1, [r4]
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add r2, r2, 0x3
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strh r2, [r4]
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mov r3, 0x1
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strb r3, [r0, 0x14]
|
||||
ldr r0, [r5]
|
||||
ldr r2, [r0, 0x1C]
|
||||
str r1, [r0]
|
||||
cmp r2, r1
|
||||
beq _081E0348
|
||||
ldrb r3, [r0, 0x4]
|
||||
ldrb r0, [r0, 0x6]
|
||||
mov r1, r2
|
||||
orr r0, r0, r3, lsl 8
|
||||
bl Callback_Dummy_S
|
||||
b _081E0348
|
||||
_081E0298:
|
||||
mov r3, 0x208
|
||||
add r3, r3, 0x4000000
|
||||
mov r2, 0
|
||||
strh r2, [r3]
|
||||
mov r1, 0x100
|
||||
add r2, r1, 0x4000002
|
||||
ldrh r3, [r2]
|
||||
tst r3, 0x80
|
||||
beq _081E031C
|
||||
ldrh r3, [r2]
|
||||
tst r3, 0x3
|
||||
bne _081E02F8
|
||||
mov r2, 0xFF00
|
||||
add r1, r1, 0x4000000
|
||||
ldrh r3, [r1]
|
||||
add r2, r2, 0x9B
|
||||
cmp r3, r2
|
||||
bls _081E031C
|
||||
_081E02E0:
|
||||
ldrh r3, [r1]
|
||||
cmp r3, r2
|
||||
bhi _081E02E0
|
||||
b _081E031C
|
||||
.align 2, 0
|
||||
_081E02F0: .4byte gSTWIStatus
|
||||
_081E02F4: .4byte 0x996601ee
|
||||
_081E02F8:
|
||||
mov r2, 0xFF00
|
||||
add r1, r1, 0x4000000
|
||||
ldrh r3, [r1]
|
||||
add r2, r2, 0xFE
|
||||
cmp r3, r2
|
||||
bls _081E031C
|
||||
_081E0310:
|
||||
ldrh r3, [r1]
|
||||
cmp r3, r2
|
||||
bhi _081E0310
|
||||
_081E031C:
|
||||
mov r1, 0x128
|
||||
add r1, r1, 0x4000000
|
||||
mov r0, 0x208
|
||||
add r0, r0, 0x4000000
|
||||
mov r3, 0x5000
|
||||
add r2, r3, 0x2
|
||||
strh r2, [r1]
|
||||
add r3, r3, 0x82
|
||||
strh r3, [r1]
|
||||
mov r2, 0x1
|
||||
strh r2, [r0]
|
||||
_081E0348:
|
||||
ldmdb r11, {r4-r6,r11,sp,lr}
|
||||
bx lr
|
||||
arm_func_end sio32intr_clock_slave
|
||||
|
||||
arm_func_start handshake_wait
|
||||
handshake_wait: @ 81E0350
|
||||
mov r12, sp
|
||||
stmdb sp!, {r11,r12,lr,pc}
|
||||
mov r1, 0x128
|
||||
add r1, r1, 0x4000000
|
||||
mov r0, r0, lsl 16
|
||||
ldr r2, _081E03B4 @ =gSTWIStatus
|
||||
sub r11, r12, 0x4
|
||||
mov lr, r0, lsr 14
|
||||
ldr r12, [r2]
|
||||
_081E0374:
|
||||
ldrb r3, [r12, 0x10]
|
||||
and r0, r3, 0xFF
|
||||
cmp r0, 0x1
|
||||
beq _081E03A0
|
||||
ldrh r3, [r1]
|
||||
and r3, r3, 0x4
|
||||
cmp r3, lr
|
||||
bne _081E0374
|
||||
mov r0, 0
|
||||
ldmdb r11, {r11,sp,lr}
|
||||
bx lr
|
||||
_081E03A0:
|
||||
ldr r2, [r2]
|
||||
mov r3, 0
|
||||
strb r3, [r2, 0x10]
|
||||
ldmdb r11, {r11,sp,lr}
|
||||
bx lr
|
||||
.align 2, 0
|
||||
_081E03B4: .4byte gSTWIStatus
|
||||
arm_func_end handshake_wait
|
||||
|
||||
arm_func_start STWI_set_timer_in_RAM
|
||||
STWI_set_timer_in_RAM: @ 81E03B8
|
||||
mov r12, sp
|
||||
stmdb sp!, {r4,r5,r11,r12,lr,pc}
|
||||
mov r1, 0x208
|
||||
add r1, r1, 0x4000000
|
||||
mov r3, 0
|
||||
sub r11, r12, 0x4
|
||||
ldr r12, _081E0470 @ =gSTWIStatus
|
||||
and lr, r0, 0xFF
|
||||
ldr r2, [r12]
|
||||
cmp lr, 0x50
|
||||
ldrb r0, [r2, 0xA]
|
||||
mov r4, r12
|
||||
mov r2, lr
|
||||
strh r3, [r1]
|
||||
mov r0, r0, lsl 2
|
||||
add r3, r3, 0x100
|
||||
add r1, r3, 0x4000000
|
||||
add r3, r3, 0x4000002
|
||||
add r5, r0, r3
|
||||
beq _081E0440
|
||||
bgt _081E0418
|
||||
cmp lr, 0x32
|
||||
beq _081E042C
|
||||
b _081E048C
|
||||
_081E0418:
|
||||
cmp r2, 0x64
|
||||
beq _081E0458
|
||||
cmp r2, 0x82
|
||||
beq _081E0474
|
||||
b _081E048C
|
||||
_081E042C:
|
||||
mvn r3, 0x334
|
||||
strh r3, [r0, r1]
|
||||
ldr r2, [r4]
|
||||
mov r3, 0x1
|
||||
b _081E0488
|
||||
_081E0440:
|
||||
mov r3, 0xAE000000
|
||||
mov r3, r3, asr 20
|
||||
strh r3, [r0, r1]
|
||||
ldr r2, [r4]
|
||||
mov r3, 0x2
|
||||
b _081E0488
|
||||
_081E0458:
|
||||
mvn r3, 0x660
|
||||
sub r3, r3, 0x9
|
||||
strh r3, [r0, r1]
|
||||
ldr r2, [r4]
|
||||
mov r3, 0x3
|
||||
b _081E0488
|
||||
.align 2, 0
|
||||
_081E0470: .4byte gSTWIStatus
|
||||
_081E0474:
|
||||
mvn r3, 0x850
|
||||
sub r3, r3, 0x2
|
||||
strh r3, [r0, r1]
|
||||
ldr r2, [r4]
|
||||
mov r3, 0x4
|
||||
_081E0488:
|
||||
str r3, [r2, 0xC]
|
||||
_081E048C:
|
||||
mov r12, 0x200
|
||||
add r12, r12, 0x4000002
|
||||
mov r3, 0xC3
|
||||
strh r3, [r5]
|
||||
mov r1, 0x208
|
||||
ldr r2, [r4]
|
||||
add r1, r1, 0x4000000
|
||||
ldrb r0, [r2, 0xA]
|
||||
sub r3, r3, 0xBB
|
||||
mov r3, r3, lsl r0
|
||||
strh r3, [r12]
|
||||
mov r2, 0x1
|
||||
strh r2, [r1]
|
||||
ldmdb r11, {r4,r5,r11,sp,lr}
|
||||
bx lr
|
||||
arm_func_end STWI_set_timer_in_RAM
|
||||
|
||||
arm_func_start STWI_stop_timer_in_RAM
|
||||
STWI_stop_timer_in_RAM: @ 81E04C8
|
||||
mov r12, sp
|
||||
stmdb sp!, {r11,r12,lr,pc}
|
||||
mov r1, 0x100
|
||||
ldr lr, _081E0514 @ =gSTWIStatus
|
||||
add r0, r1, 0x4000000
|
||||
ldr r2, [lr]
|
||||
sub r11, r12, 0x4
|
||||
ldrb r3, [r2, 0xA]
|
||||
mov r12, 0
|
||||
str r12, [r2, 0xC]
|
||||
mov r3, r3, lsl 2
|
||||
strh r12, [r3, r0]
|
||||
ldr r2, [lr]
|
||||
ldrb r3, [r2, 0xA]
|
||||
add r1, r1, 0x4000002
|
||||
mov r3, r3, lsl 2
|
||||
strh r12, [r3, r1]
|
||||
ldmdb r11, {r11,sp,lr}
|
||||
bx lr
|
||||
.align 2, 0
|
||||
_081E0514: .4byte gSTWIStatus
|
||||
arm_func_end STWI_stop_timer_in_RAM
|
||||
|
||||
arm_func_start STWI_init_slave
|
||||
STWI_init_slave: @ 81E0518
|
||||
mov r12, sp
|
||||
stmdb sp!, {r11,r12,lr,pc}
|
||||
ldr r0, _081E05A0 @ =gSTWIStatus
|
||||
ldr r2, [r0]
|
||||
mov r3, 0x5
|
||||
str r3, [r2]
|
||||
mov r1, 0
|
||||
strb r1, [r2, 0x14]
|
||||
ldr r3, [r0]
|
||||
strb r1, [r3, 0x4]
|
||||
ldr r2, [r0]
|
||||
strb r1, [r2, 0x5]
|
||||
ldr r3, [r0]
|
||||
strb r1, [r3, 0x6]
|
||||
ldr r2, [r0]
|
||||
strb r1, [r2, 0x7]
|
||||
ldr r3, [r0]
|
||||
strb r1, [r3, 0x8]
|
||||
ldr r2, [r0]
|
||||
strb r1, [r2, 0x9]
|
||||
ldr r3, [r0]
|
||||
str r1, [r3, 0xC]
|
||||
sub r11, r12, 0x4
|
||||
strb r1, [r3, 0x10]
|
||||
mov r2, 0x128
|
||||
ldr r12, [r0]
|
||||
add r2, r2, 0x4000000
|
||||
strh r1, [r12, 0x12]
|
||||
mov r3, 0x5000
|
||||
strb r1, [r12, 0x15]
|
||||
add r3, r3, 0x82
|
||||
strh r3, [r2]
|
||||
ldmdb r11, {r11,sp,lr}
|
||||
bx lr
|
||||
.align 2, 0
|
||||
_081E05A0: .4byte gSTWIStatus
|
||||
arm_func_end STWI_init_slave
|
||||
|
||||
arm_func_start Callback_Dummy_M
|
||||
Callback_Dummy_M: @ 81E05A4
|
||||
bx r2
|
||||
arm_func_end Callback_Dummy_M
|
||||
|
||||
arm_func_start Callback_Dummy_S
|
||||
Callback_Dummy_S: @ 81E05A8
|
||||
bx r1
|
||||
arm_func_end Callback_Dummy_S
|
||||
|
||||
arm_func_start Callback_Dummy_ID
|
||||
Callback_Dummy_ID: @ 81E05AC
|
||||
bx r0
|
||||
arm_func_end Callback_Dummy_ID
|
||||
|
||||
+1
-1
@@ -20,7 +20,7 @@ else
|
||||
exit 1
|
||||
fi
|
||||
|
||||
OBJDUMP="$DEVKITARM/bin/arm-none-eabi-objdump -D -bbinary -marmv4t -Mforce-thumb"
|
||||
OBJDUMP="$DEVKITARM/bin/arm-none-eabi-objdump -D -bbinary -marmv4t"
|
||||
OPTIONS="--start-address=$(($1)) --stop-address=$(($1 + $2))"
|
||||
$OBJDUMP $OPTIONS ${baserom}.gba > ${baserom}.dump || exit 1
|
||||
$OBJDUMP $OPTIONS poke${buildname}.gba > poke${buildname}.dump
|
||||
|
||||
+1
-1
@@ -315,7 +315,7 @@ struct STWIStatus
|
||||
u8 unk_17;
|
||||
void (*callbackM)();
|
||||
void (*callbackS)(u16);
|
||||
void (*unk_20)(void);
|
||||
void (*callbackID)(void);
|
||||
union RfuPacket *txPacket;
|
||||
union RfuPacket *rxPacket;
|
||||
vu8 unk_2c;
|
||||
|
||||
@@ -322,6 +322,7 @@ SECTIONS {
|
||||
src/agb_flash_mx.o(.text);
|
||||
src/agb_flash_le.o(.text);
|
||||
src/librfu_stwi.o(.text);
|
||||
src/librfu_intr.o(.text);
|
||||
asm/librfu_intr.o(.text);
|
||||
src/librfu_rfu.o(.text);
|
||||
src/librfu_sio32id.o(.text);
|
||||
|
||||
@@ -0,0 +1,403 @@
|
||||
#include "global.h"
|
||||
#include "librfu.h"
|
||||
|
||||
static void sio32intr_clock_master(void);
|
||||
static void sio32intr_clock_slave(void);
|
||||
static u16 handshake_wait(u16 slot);
|
||||
static void STWI_set_timer_in_RAM(u8 count);
|
||||
static void STWI_stop_timer_in_RAM(void);
|
||||
static void STWI_init_slave(void);
|
||||
static void Callback_Dummy_M(int reqCommandId, int error, void (*callbackM)());
|
||||
static void Callback_Dummy_S(u16 reqCommandId, void (*callbackS)(u16));
|
||||
static void Callback_Dummy_ID(void (*callbackId)(void));
|
||||
|
||||
void IntrSIO32(void)
|
||||
{
|
||||
if (gSTWIStatus->state == 10)
|
||||
{
|
||||
if (gSTWIStatus->callbackID != NULL)
|
||||
Callback_Dummy_ID(gSTWIStatus->callbackID);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (gSTWIStatus->msMode == AGB_CLK_MASTER)
|
||||
sio32intr_clock_master();
|
||||
else
|
||||
sio32intr_clock_slave();
|
||||
}
|
||||
}
|
||||
|
||||
static void sio32intr_clock_master(void)
|
||||
{
|
||||
u32 regSIODATA32;
|
||||
u32 ackLen;
|
||||
|
||||
STWI_set_timer_in_RAM(80);
|
||||
regSIODATA32 = REG_SIODATA32;
|
||||
|
||||
if (gSTWIStatus->state == 0)
|
||||
{
|
||||
if (regSIODATA32 == 0x80000000)
|
||||
{
|
||||
if (gSTWIStatus->reqNext <= gSTWIStatus->reqLength)
|
||||
{
|
||||
REG_SIODATA32 = ((u32*)gSTWIStatus->txPacket->rfuPacket8.data)[gSTWIStatus->reqNext];
|
||||
gSTWIStatus->reqNext++;
|
||||
}
|
||||
else
|
||||
{
|
||||
gSTWIStatus->state = 1;
|
||||
REG_SIODATA32 = 0x80000000;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
STWI_stop_timer_in_RAM();
|
||||
STWI_set_timer_in_RAM(130);
|
||||
return;
|
||||
}
|
||||
}
|
||||
else if (gSTWIStatus->state == 1)
|
||||
{
|
||||
if ((regSIODATA32 & 0xFFFF0000) == 0x99660000)
|
||||
{
|
||||
gSTWIStatus->ackNext = 0;
|
||||
((u32*)gSTWIStatus->rxPacket)[gSTWIStatus->ackNext] = regSIODATA32;
|
||||
gSTWIStatus->ackNext++;
|
||||
gSTWIStatus->ackActiveCommand = regSIODATA32;
|
||||
gSTWIStatus->ackLength = ackLen = regSIODATA32 >> 8;
|
||||
if ((ackLen = gSTWIStatus->ackLength) >= gSTWIStatus->ackNext)
|
||||
{
|
||||
gSTWIStatus->state = 2;
|
||||
REG_SIODATA32 = 0x80000000;
|
||||
}
|
||||
else
|
||||
{
|
||||
gSTWIStatus->state = 3;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
STWI_stop_timer_in_RAM();
|
||||
STWI_set_timer_in_RAM(130);
|
||||
return;
|
||||
}
|
||||
}
|
||||
else if (gSTWIStatus->state == 2)
|
||||
{
|
||||
((u32*)gSTWIStatus->rxPacket)[gSTWIStatus->ackNext] = regSIODATA32;
|
||||
gSTWIStatus->ackNext++;
|
||||
if (gSTWIStatus->ackLength < gSTWIStatus->ackNext)
|
||||
gSTWIStatus->state = 3;
|
||||
else
|
||||
REG_SIODATA32 = 0x80000000;
|
||||
}
|
||||
|
||||
if (handshake_wait(1) == 1)
|
||||
return;
|
||||
|
||||
REG_SIOCNT = 0x500B;
|
||||
|
||||
if (handshake_wait(0) == 1)
|
||||
return;
|
||||
|
||||
STWI_stop_timer_in_RAM();
|
||||
|
||||
if (gSTWIStatus->state == 3)
|
||||
{
|
||||
if (
|
||||
gSTWIStatus->ackActiveCommand == (0x80 | ID_MS_CHANGE_REQ)
|
||||
|| gSTWIStatus->ackActiveCommand == (0x80 | ID_DATA_TX_AND_CHANGE_REQ)
|
||||
|| gSTWIStatus->ackActiveCommand == (0x80 | ID_UNK35_REQ)
|
||||
|| gSTWIStatus->ackActiveCommand == (0x80 | ID_RESUME_RETRANSMIT_AND_CHANGE_REQ)
|
||||
)
|
||||
{
|
||||
|
||||
gSTWIStatus->msMode = 0;
|
||||
REG_SIODATA32 = 0x80000000;
|
||||
REG_SIOCNT = 0x5002;
|
||||
REG_SIOCNT = 0x5082;
|
||||
gSTWIStatus->state = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
if (gSTWIStatus->ackActiveCommand == 238)
|
||||
{
|
||||
REG_SIOCNT = 0x5003;
|
||||
gSTWIStatus->state = 4;
|
||||
gSTWIStatus->error = ERR_REQ_CMD_ACK_REJECTION;
|
||||
}
|
||||
else
|
||||
{
|
||||
REG_SIOCNT = 0x5003;
|
||||
gSTWIStatus->state = 4;
|
||||
}
|
||||
}
|
||||
gSTWIStatus->unk_2c = 0;
|
||||
if (gSTWIStatus->callbackM != NULL)
|
||||
Callback_Dummy_M(gSTWIStatus->reqActiveCommand, gSTWIStatus->error, gSTWIStatus->callbackM);
|
||||
}
|
||||
else
|
||||
{
|
||||
REG_SIOCNT = 0x5003;
|
||||
REG_SIOCNT = 0x5083;
|
||||
}
|
||||
}
|
||||
|
||||
static void sio32intr_clock_slave(void)
|
||||
{
|
||||
u32 regSIODATA32;
|
||||
u32 r0;
|
||||
register u32 reqLen asm("r2");
|
||||
|
||||
gSTWIStatus->timerActive = 0;
|
||||
STWI_set_timer_in_RAM(100);
|
||||
if (handshake_wait(0) == 1)
|
||||
return;
|
||||
REG_SIOCNT = 0x500A;
|
||||
regSIODATA32 = REG_SIODATA32;
|
||||
if (gSTWIStatus->state == 5)
|
||||
{
|
||||
((u32*)gSTWIStatus->rxPacket)[0] = regSIODATA32;
|
||||
gSTWIStatus->reqNext = 1;
|
||||
r0 = 0x99660000;
|
||||
if ((regSIODATA32 >> 16) == (r0 >> 16))
|
||||
{
|
||||
gSTWIStatus->reqLength = reqLen = regSIODATA32 >> 8;
|
||||
gSTWIStatus->reqActiveCommand = regSIODATA32;
|
||||
if (gSTWIStatus->reqLength == 0)
|
||||
{
|
||||
if (
|
||||
gSTWIStatus->reqActiveCommand == 0x0027
|
||||
|| gSTWIStatus->reqActiveCommand == 0x0028
|
||||
|| gSTWIStatus->reqActiveCommand == 0x0029
|
||||
|| gSTWIStatus->reqActiveCommand == 0x0036
|
||||
)
|
||||
{
|
||||
gSTWIStatus->ackActiveCommand = gSTWIStatus->reqActiveCommand + 0x80;
|
||||
((u32*)gSTWIStatus->txPacket)[0] = 0x99660000 + gSTWIStatus->ackActiveCommand;
|
||||
gSTWIStatus->ackLength = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
((u32*)gSTWIStatus->txPacket)[0] = 0x996601EE;
|
||||
if (gSTWIStatus->reqActiveCommand >= 0x10 && gSTWIStatus->reqActiveCommand <= 0x3D)
|
||||
{
|
||||
((u32*)gSTWIStatus->txPacket)[1] = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
((u32*)gSTWIStatus->txPacket)[1] = 2;
|
||||
}
|
||||
gSTWIStatus->ackLength = 1;
|
||||
gSTWIStatus->error = 3;
|
||||
}
|
||||
REG_SIODATA32 = ((u32*)gSTWIStatus->txPacket)[0];
|
||||
gSTWIStatus->ackNext = 1;
|
||||
gSTWIStatus->state = 7;
|
||||
}
|
||||
else
|
||||
{
|
||||
REG_SIODATA32 = 0x80000000;
|
||||
gSTWIStatus->reqNext = 1;
|
||||
gSTWIStatus->state = 6;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
STWI_stop_timer_in_RAM();
|
||||
STWI_set_timer_in_RAM(100);
|
||||
return;
|
||||
}
|
||||
}
|
||||
else if (gSTWIStatus->state == 6)
|
||||
{
|
||||
((u32*)gSTWIStatus->rxPacket)[gSTWIStatus->reqNext] = regSIODATA32;
|
||||
gSTWIStatus->reqNext++;
|
||||
if (gSTWIStatus->reqLength < gSTWIStatus->reqNext)
|
||||
{
|
||||
if (
|
||||
gSTWIStatus->reqActiveCommand == 0x0028
|
||||
|| gSTWIStatus->reqActiveCommand == 0x0029
|
||||
|| gSTWIStatus->reqActiveCommand == 0x0036
|
||||
)
|
||||
{
|
||||
gSTWIStatus->ackActiveCommand = gSTWIStatus->reqActiveCommand + 0x80;
|
||||
((u32*)gSTWIStatus->txPacket)[0] = 0x99660000 | gSTWIStatus->ackActiveCommand;
|
||||
gSTWIStatus->ackLength = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
((u32*)gSTWIStatus->txPacket)[0] = 0x996601EE;
|
||||
if (gSTWIStatus->reqActiveCommand >= 0x10 && gSTWIStatus->reqActiveCommand <= 0x3D)
|
||||
{
|
||||
((u32*)gSTWIStatus->txPacket)[1] = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
((u32*)gSTWIStatus->txPacket)[1] = 2;
|
||||
}
|
||||
gSTWIStatus->ackLength = 1;
|
||||
gSTWIStatus->error = 3;
|
||||
}
|
||||
REG_SIODATA32 = ((u32*)gSTWIStatus->txPacket)[0];
|
||||
gSTWIStatus->ackNext = 1;
|
||||
gSTWIStatus->state = 7;
|
||||
}
|
||||
else
|
||||
{
|
||||
REG_SIODATA32 = 0x80000000;
|
||||
}
|
||||
}
|
||||
else if (gSTWIStatus->state == 7)
|
||||
{
|
||||
if (regSIODATA32 == 0x80000000)
|
||||
{
|
||||
if (gSTWIStatus->ackLength < gSTWIStatus->ackNext)
|
||||
{
|
||||
gSTWIStatus->state = 8;
|
||||
}
|
||||
else
|
||||
{
|
||||
REG_SIODATA32 = ((u32*)gSTWIStatus->txPacket)[gSTWIStatus->ackNext];
|
||||
gSTWIStatus->ackNext++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
STWI_stop_timer_in_RAM();
|
||||
STWI_set_timer_in_RAM(100);
|
||||
return;
|
||||
}
|
||||
}
|
||||
if (handshake_wait(1) == 1)
|
||||
return;
|
||||
if (gSTWIStatus->state == 8)
|
||||
{
|
||||
REG_SIOCNT = 0x5002;
|
||||
STWI_stop_timer_in_RAM();
|
||||
if (gSTWIStatus->error == 3)
|
||||
{
|
||||
STWI_init_slave();
|
||||
if (gSTWIStatus->callbackS != NULL)
|
||||
{
|
||||
Callback_Dummy_S(0x1EE, gSTWIStatus->callbackS);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
REG_SIODATA32 = 0;
|
||||
REG_SIOCNT = 0;
|
||||
REG_SIOCNT = 0x5003;
|
||||
gSTWIStatus->msMode = AGB_CLK_MASTER;
|
||||
gSTWIStatus->state = 0;
|
||||
if (gSTWIStatus->callbackS != NULL)
|
||||
{
|
||||
Callback_Dummy_S((gSTWIStatus->reqLength << 8) | (gSTWIStatus->reqActiveCommand), gSTWIStatus->callbackS);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
REG_IME = 0;
|
||||
if (REG_TM0CNT_H & 0x80)
|
||||
{
|
||||
if (!(REG_TM0CNT_H & 0x03))
|
||||
{
|
||||
while (REG_TM0CNT_L > 0xFF9B);
|
||||
}
|
||||
else
|
||||
{
|
||||
while (REG_TM0CNT_L > 0xFFFE);
|
||||
}
|
||||
}
|
||||
REG_SIOCNT = 0x5002;
|
||||
REG_SIOCNT = 0x5082;
|
||||
REG_IME = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static u16 handshake_wait(u16 slot)
|
||||
{
|
||||
do
|
||||
{
|
||||
if ((gSTWIStatus->timerActive & 0xFF) == 1)
|
||||
{
|
||||
gSTWIStatus->timerActive = 0;
|
||||
return 1;
|
||||
}
|
||||
} while ((REG_SIOCNT & 4) != (slot << 2));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void STWI_set_timer_in_RAM(u8 count)
|
||||
{
|
||||
vu16* regTMCNTL = (vu16*)(REG_ADDR_TMCNT_L + gSTWIStatus->timerSelect * 4);
|
||||
vu16* regTMCNTH = (vu16*)(REG_ADDR_TMCNT_H + gSTWIStatus->timerSelect * 4);
|
||||
REG_IME = 0;
|
||||
switch (count)
|
||||
{
|
||||
case 50:
|
||||
*regTMCNTL = -0x335;
|
||||
gSTWIStatus->timerState = 1;
|
||||
break;
|
||||
case 80:
|
||||
*regTMCNTL = -0x520;
|
||||
gSTWIStatus->timerState = 2;
|
||||
break;
|
||||
case 100:
|
||||
*regTMCNTL = -0x66a;
|
||||
gSTWIStatus->timerState = 3;
|
||||
break;
|
||||
case 130:
|
||||
*regTMCNTL = -0x853;
|
||||
gSTWIStatus->timerState = 4;
|
||||
break;
|
||||
}
|
||||
*regTMCNTH = TIMER_ENABLE | TIMER_64CLK | TIMER_256CLK | TIMER_INTR_ENABLE;
|
||||
REG_IF = INTR_FLAG_TIMER0 << gSTWIStatus->timerSelect;
|
||||
REG_IME = 1;
|
||||
}
|
||||
|
||||
static void STWI_stop_timer_in_RAM(void)
|
||||
{
|
||||
gSTWIStatus->timerState = 0;
|
||||
REG_TMCNT_L(gSTWIStatus->timerSelect) = 0;
|
||||
REG_TMCNT_H(gSTWIStatus->timerSelect) = 0;
|
||||
}
|
||||
|
||||
static void STWI_init_slave(void)
|
||||
{
|
||||
gSTWIStatus->state = 5;
|
||||
gSTWIStatus->msMode = 0;
|
||||
gSTWIStatus->reqLength = 0;
|
||||
gSTWIStatus->reqNext = 0;
|
||||
gSTWIStatus->reqActiveCommand = 0;
|
||||
gSTWIStatus->ackLength = 0;
|
||||
gSTWIStatus->ackNext = 0;
|
||||
gSTWIStatus->ackActiveCommand = 0;
|
||||
gSTWIStatus->timerState = 0;
|
||||
gSTWIStatus->timerActive = 0;
|
||||
gSTWIStatus->error = 0;
|
||||
gSTWIStatus->recoveryCount = 0;
|
||||
REG_SIOCNT = 0x5082;
|
||||
}
|
||||
|
||||
NAKED
|
||||
static void Callback_Dummy_M(int reqCommandId, int error, void (*callbackM)())
|
||||
{
|
||||
asm("bx r2");
|
||||
}
|
||||
|
||||
NAKED
|
||||
static void Callback_Dummy_S(u16 reqCommandId, void (*callbackS)(u16))
|
||||
{
|
||||
asm("bx r1");
|
||||
}
|
||||
|
||||
NAKED
|
||||
static void Callback_Dummy_ID(void (*callbackId)(void))
|
||||
{
|
||||
asm("bx r0");
|
||||
}
|
||||
+1
-1
@@ -131,7 +131,7 @@ void STWI_set_Callback_S(void (*callbackS)(u16))
|
||||
|
||||
void STWI_set_Callback_ID(void (*func)(void)) // name in SDK, but is actually setting a function pointer
|
||||
{
|
||||
gSTWIStatus->unk_20 = func;
|
||||
gSTWIStatus->callbackID = func;
|
||||
}
|
||||
|
||||
u16 STWI_poll_CommandEnd(void)
|
||||
|
||||
Reference in New Issue
Block a user