decompile gpu_regs
This commit is contained in:
sceptillion
-373
@@ -1,373 +0,0 @@
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.include "asm/macros.inc"
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.include "constants/constants.inc"
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.syntax unified
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.text
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thumb_func_start InitGpuRegManager
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InitGpuRegManager: @ 8000968
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push {r4-r7,lr}
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mov r7, r8
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push {r7}
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movs r2, 0
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ldr r7, _080009AC @ =gUnknown_30000C0
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ldr r0, _080009B0 @ =gUnknown_30000C1
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mov r12, r0
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ldr r1, _080009B4 @ =gUnknown_30000C2
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mov r8, r1
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ldr r6, _080009B8 @ =gUnknown_3000000
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movs r5, 0
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ldr r4, _080009BC @ =gUnknown_3000060
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movs r3, 0xFF
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_08000982:
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adds r0, r2, r6
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strb r5, [r0]
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adds r1, r2, r4
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ldrb r0, [r1]
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orrs r0, r3
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strb r0, [r1]
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adds r2, 0x1
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cmp r2, 0x5F
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ble _08000982
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movs r0, 0
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strb r0, [r7]
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mov r1, r12
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strb r0, [r1]
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movs r0, 0
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mov r1, r8
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strh r0, [r1]
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pop {r3}
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mov r8, r3
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pop {r4-r7}
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pop {r0}
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bx r0
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.align 2, 0
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_080009AC: .4byte gUnknown_30000C0
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_080009B0: .4byte gUnknown_30000C1
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_080009B4: .4byte gUnknown_30000C2
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_080009B8: .4byte gUnknown_3000000
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_080009BC: .4byte gUnknown_3000060
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thumb_func_end InitGpuRegManager
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thumb_func_start CopyBufferedValueToGpuReg
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CopyBufferedValueToGpuReg: @ 80009C0
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push {lr}
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lsls r0, 24
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lsrs r2, r0, 24
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cmp r2, 0x4
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bne _080009EC
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ldr r2, _080009E0 @ =0x04000004
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ldrh r1, [r2]
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ldr r0, _080009E4 @ =0x0000ffe7
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ands r0, r1
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strh r0, [r2]
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ldr r1, _080009E8 @ =gUnknown_3000004
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ldrh r0, [r2]
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ldrh r1, [r1]
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orrs r0, r1
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strh r0, [r2]
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b _080009FA
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.align 2, 0
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_080009E0: .4byte 0x04000004
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_080009E4: .4byte 0x0000ffe7
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_080009E8: .4byte gUnknown_3000004
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_080009EC:
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movs r0, 0x80
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lsls r0, 19
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adds r0, r2, r0
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ldr r1, _08000A00 @ =gUnknown_3000000
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adds r1, r2, r1
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ldrh r1, [r1]
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strh r1, [r0]
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_080009FA:
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pop {r0}
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bx r0
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.align 2, 0
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_08000A00: .4byte gUnknown_3000000
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thumb_func_end CopyBufferedValueToGpuReg
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thumb_func_start CopyBufferedValuesToGpuRegs
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CopyBufferedValuesToGpuRegs: @ 8000A04
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push {r4,r5,lr}
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ldr r0, _08000A30 @ =gUnknown_30000C0
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ldrb r0, [r0]
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cmp r0, 0
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bne _08000A28
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movs r5, 0
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_08000A10:
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ldr r0, _08000A34 @ =gUnknown_3000060
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adds r4, r5, r0
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ldrb r0, [r4]
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cmp r0, 0xFF
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beq _08000A28
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bl CopyBufferedValueToGpuReg
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movs r0, 0xFF
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strb r0, [r4]
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adds r5, 0x1
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cmp r5, 0x5F
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ble _08000A10
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_08000A28:
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pop {r4,r5}
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pop {r0}
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bx r0
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.align 2, 0
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_08000A30: .4byte gUnknown_30000C0
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_08000A34: .4byte gUnknown_3000060
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thumb_func_end CopyBufferedValuesToGpuRegs
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thumb_func_start SetGpuReg
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SetGpuReg: @ 8000A38
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push {r4,r5,lr}
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lsls r0, 24
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lsrs r4, r0, 24
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lsls r1, 16
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lsrs r1, 16
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cmp r4, 0x5F
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bhi _08000AB4
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ldr r0, _08000A74 @ =gUnknown_3000000
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adds r0, r4, r0
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strh r1, [r0]
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ldr r0, _08000A78 @ =0x04000006
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ldrh r1, [r0]
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movs r0, 0xFF
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ands r0, r1
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subs r0, 0xA1
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lsls r0, 16
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lsrs r0, 16
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cmp r0, 0x40
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bls _08000A6C
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movs r0, 0x80
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lsls r0, 19
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ldrh r1, [r0]
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movs r0, 0x80
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ands r0, r1
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cmp r0, 0
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beq _08000A82
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_08000A6C:
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adds r0, r4, 0
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bl CopyBufferedValueToGpuReg
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b _08000AB4
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.align 2, 0
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_08000A74: .4byte gUnknown_3000000
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_08000A78: .4byte 0x04000006
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_08000A7C:
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movs r0, 0
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strb r0, [r5]
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b _08000AB4
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_08000A82:
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ldr r2, _08000ABC @ =gUnknown_30000C0
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movs r0, 0x1
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strb r0, [r2]
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movs r3, 0
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ldr r0, _08000AC0 @ =gUnknown_3000060
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ldrb r1, [r0]
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adds r5, r2, 0
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adds r2, r0, 0
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cmp r1, 0xFF
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beq _08000AAC
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adds r1, r2, 0
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_08000A98:
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ldrb r0, [r1]
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cmp r0, r4
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beq _08000A7C
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adds r1, 0x1
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adds r3, 0x1
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cmp r3, 0x5F
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bgt _08000AAC
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ldrb r0, [r1]
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cmp r0, 0xFF
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bne _08000A98
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_08000AAC:
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adds r0, r3, r2
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movs r1, 0
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strb r4, [r0]
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strb r1, [r5]
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_08000AB4:
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pop {r4,r5}
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pop {r0}
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bx r0
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.align 2, 0
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_08000ABC: .4byte gUnknown_30000C0
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_08000AC0: .4byte gUnknown_3000060
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thumb_func_end SetGpuReg
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thumb_func_start GetGpuReg
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GetGpuReg: @ 8000AC4
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push {lr}
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lsls r0, 24
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lsrs r0, 24
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adds r1, r0, 0
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cmp r1, 0x4
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bne _08000AD8
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ldr r0, _08000AD4 @ =0x04000004
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b _08000AEA
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.align 2, 0
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_08000AD4: .4byte 0x04000004
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_08000AD8:
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cmp r1, 0x6
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beq _08000AE8
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ldr r0, _08000AE4 @ =gUnknown_3000000
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adds r0, r1, r0
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ldrh r0, [r0]
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b _08000AEC
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.align 2, 0
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_08000AE4: .4byte gUnknown_3000000
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_08000AE8:
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ldr r0, _08000AF0 @ =0x04000006
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_08000AEA:
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ldrh r0, [r0]
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_08000AEC:
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pop {r1}
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bx r1
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.align 2, 0
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_08000AF0: .4byte 0x04000006
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thumb_func_end GetGpuReg
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thumb_func_start SetGpuRegBits
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SetGpuRegBits: @ 8000AF4
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push {lr}
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adds r2, r1, 0
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lsls r0, 24
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lsrs r0, 24
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ldr r1, _08000B10 @ =gUnknown_3000000
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adds r1, r0, r1
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ldrh r1, [r1]
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orrs r1, r2
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lsls r1, 16
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lsrs r1, 16
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bl SetGpuReg
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pop {r0}
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bx r0
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.align 2, 0
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_08000B10: .4byte gUnknown_3000000
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thumb_func_end SetGpuRegBits
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thumb_func_start ClearGpuRegBits
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ClearGpuRegBits: @ 8000B14
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push {lr}
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adds r2, r1, 0
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lsls r0, 24
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lsrs r0, 24
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lsls r2, 16
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ldr r1, _08000B30 @ =gUnknown_3000000
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adds r1, r0, r1
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ldrh r1, [r1]
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lsrs r2, 16
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bics r1, r2
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bl SetGpuReg
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pop {r0}
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bx r0
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.align 2, 0
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_08000B30: .4byte gUnknown_3000000
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thumb_func_end ClearGpuRegBits
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thumb_func_start SyncRegIE
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SyncRegIE: @ 8000B34
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push {r4,r5,lr}
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ldr r5, _08000B58 @ =gUnknown_30000C1
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ldrb r0, [r5]
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cmp r0, 0
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beq _08000B52
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ldr r2, _08000B5C @ =0x04000208
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ldrh r1, [r2]
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movs r4, 0
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strh r4, [r2]
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ldr r3, _08000B60 @ =0x04000200
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ldr r0, _08000B64 @ =gUnknown_30000C2
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ldrh r0, [r0]
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strh r0, [r3]
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strh r1, [r2]
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strb r4, [r5]
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_08000B52:
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pop {r4,r5}
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pop {r0}
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bx r0
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.align 2, 0
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_08000B58: .4byte gUnknown_30000C1
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_08000B5C: .4byte 0x04000208
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_08000B60: .4byte 0x04000200
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_08000B64: .4byte gUnknown_30000C2
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thumb_func_end SyncRegIE
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thumb_func_start EnableInterrupts
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EnableInterrupts: @ 8000B68
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push {r4,lr}
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lsls r0, 16
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lsrs r0, 16
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ldr r4, _08000B8C @ =gUnknown_30000C2
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ldrh r1, [r4]
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orrs r0, r1
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strh r0, [r4]
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ldr r1, _08000B90 @ =gUnknown_30000C1
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movs r0, 0x1
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strb r0, [r1]
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bl SyncRegIE
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ldrh r0, [r4]
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bl UpdateRegDispstatIntrBits
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pop {r4}
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pop {r0}
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bx r0
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.align 2, 0
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_08000B8C: .4byte gUnknown_30000C2
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_08000B90: .4byte gUnknown_30000C1
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thumb_func_end EnableInterrupts
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thumb_func_start DisableInterrupts
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DisableInterrupts: @ 8000B94
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push {r4,lr}
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lsls r0, 16
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lsrs r0, 16
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ldr r4, _08000BB8 @ =gUnknown_30000C2
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ldrh r1, [r4]
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bics r1, r0
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strh r1, [r4]
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ldr r1, _08000BBC @ =gUnknown_30000C1
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movs r0, 0x1
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strb r0, [r1]
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bl SyncRegIE
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ldrh r0, [r4]
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bl UpdateRegDispstatIntrBits
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pop {r4}
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pop {r0}
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bx r0
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.align 2, 0
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_08000BB8: .4byte gUnknown_30000C2
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_08000BBC: .4byte gUnknown_30000C1
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thumb_func_end DisableInterrupts
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thumb_func_start UpdateRegDispstatIntrBits
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UpdateRegDispstatIntrBits: @ 8000BC0
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push {r4,lr}
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adds r4, r0, 0
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lsls r4, 16
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lsrs r4, 16
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movs r0, 0x4
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bl GetGpuReg
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movs r2, 0x18
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ands r2, r0
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movs r1, 0x1
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ands r1, r4
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negs r0, r1
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orrs r0, r1
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asrs r1, r0, 31
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movs r0, 0x8
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ands r1, r0
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movs r0, 0x2
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ands r0, r4
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cmp r0, 0
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beq _08000BEC
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movs r0, 0x10
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orrs r1, r0
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_08000BEC:
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cmp r2, r1
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beq _08000BF6
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movs r0, 0x4
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bl SetGpuReg
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_08000BF6:
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pop {r4}
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pop {r0}
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bx r0
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thumb_func_end UpdateRegDispstatIntrBits
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.align 2, 0 @ Don't pad with nop.
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+1
-1
@@ -83,7 +83,7 @@ SECTIONS {
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{
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asm/crt0.o(.text);
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src/main.o(.text);
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asm/gpu_regs.o(.text);
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src/gpu_regs.o(.text);
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asm/dma3_manager.o(.text);
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asm/bg.o(.text);
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asm/malloc.o(.text);
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+159
@@ -0,0 +1,159 @@
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#include "global.h"
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#include "gpu_regs.h"
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#define GPU_REG_BUF_SIZE 0x60
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#define GPU_REG_BUF(offset) (*(u16 *)(&sGpuRegBuffer[offset]))
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#define GPU_REG(offset) (*(vu16 *)(REG_BASE + offset))
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#define EMPTY_SLOT 0xFF
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static u8 sGpuRegBuffer[GPU_REG_BUF_SIZE];
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static u8 sGpuRegWaitingList[GPU_REG_BUF_SIZE];
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static bool8 sGpuRegBufferLocked;
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static bool8 sShouldSyncRegIE;
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static u16 sRegIE;
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static void CopyBufferedValueToGpuReg(u8 regOffset);
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static void SyncRegIE(void);
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static void UpdateRegDispstatIntrBits(u16 regIE);
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void InitGpuRegManager(void)
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{
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s32 i;
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for (i = 0; i < GPU_REG_BUF_SIZE; i++)
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{
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sGpuRegBuffer[i] = 0;
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sGpuRegWaitingList[i] = EMPTY_SLOT;
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}
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sGpuRegBufferLocked = FALSE;
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sShouldSyncRegIE = FALSE;
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sRegIE = 0;
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}
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static void CopyBufferedValueToGpuReg(u8 regOffset)
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{
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if (regOffset == REG_OFFSET_DISPSTAT)
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{
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REG_DISPSTAT &= ~(DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
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REG_DISPSTAT |= GPU_REG_BUF(REG_OFFSET_DISPSTAT);
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}
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else
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{
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GPU_REG(regOffset) = GPU_REG_BUF(regOffset);
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}
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}
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void CopyBufferedValuesToGpuRegs(void)
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{
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if (!sGpuRegBufferLocked)
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{
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s32 i;
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for (i = 0; i < GPU_REG_BUF_SIZE; i++)
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{
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u8 regOffset = sGpuRegWaitingList[i];
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if (regOffset == EMPTY_SLOT)
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return;
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CopyBufferedValueToGpuReg(regOffset);
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sGpuRegWaitingList[i] = EMPTY_SLOT;
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}
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}
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}
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void SetGpuReg(u8 regOffset, u16 value)
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{
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if (regOffset < GPU_REG_BUF_SIZE)
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{
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u16 vcount;
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GPU_REG_BUF(regOffset) = value;
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vcount = REG_VCOUNT & 0xFF;
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if ((vcount >= 161 && vcount <= 225)
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|| (REG_DISPCNT & DISPCNT_FORCED_BLANK)) {
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CopyBufferedValueToGpuReg(regOffset);
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} else {
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s32 i;
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sGpuRegBufferLocked = TRUE;
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for (i = 0; i < GPU_REG_BUF_SIZE && sGpuRegWaitingList[i] != EMPTY_SLOT; i++) {
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if (sGpuRegWaitingList[i] == regOffset) {
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sGpuRegBufferLocked = FALSE;
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return;
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}
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}
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sGpuRegWaitingList[i] = regOffset;
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sGpuRegBufferLocked = FALSE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
u16 GetGpuReg(u8 regOffset)
|
||||
{
|
||||
if (regOffset == REG_OFFSET_DISPSTAT)
|
||||
return REG_DISPSTAT;
|
||||
|
||||
if (regOffset == REG_OFFSET_VCOUNT)
|
||||
return REG_VCOUNT;
|
||||
|
||||
return GPU_REG_BUF(regOffset);
|
||||
}
|
||||
|
||||
void SetGpuRegBits(u8 regOffset, u16 mask)
|
||||
{
|
||||
u16 regValue = GPU_REG_BUF(regOffset);
|
||||
SetGpuReg(regOffset, regValue | mask);
|
||||
}
|
||||
|
||||
void ClearGpuRegBits(u8 regOffset, u16 mask)
|
||||
{
|
||||
u16 regValue = GPU_REG_BUF(regOffset);
|
||||
SetGpuReg(regOffset, regValue & ~mask);
|
||||
}
|
||||
|
||||
static void SyncRegIE(void)
|
||||
{
|
||||
if (sShouldSyncRegIE) {
|
||||
u16 temp = REG_IME;
|
||||
REG_IME = 0;
|
||||
REG_IE = sRegIE;
|
||||
REG_IME = temp;
|
||||
sShouldSyncRegIE = FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
void EnableInterrupts(u16 mask)
|
||||
{
|
||||
sRegIE |= mask;
|
||||
sShouldSyncRegIE = TRUE;
|
||||
SyncRegIE();
|
||||
UpdateRegDispstatIntrBits(sRegIE);
|
||||
}
|
||||
|
||||
void DisableInterrupts(u16 mask)
|
||||
{
|
||||
sRegIE &= ~mask;
|
||||
sShouldSyncRegIE = TRUE;
|
||||
SyncRegIE();
|
||||
UpdateRegDispstatIntrBits(sRegIE);
|
||||
}
|
||||
|
||||
static void UpdateRegDispstatIntrBits(u16 regIE)
|
||||
{
|
||||
u16 oldValue = GetGpuReg(REG_OFFSET_DISPSTAT) & (DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
|
||||
u16 newValue = 0;
|
||||
|
||||
if (regIE & INTR_FLAG_VBLANK)
|
||||
newValue |= DISPSTAT_VBLANK_INTR;
|
||||
|
||||
if (regIE & INTR_FLAG_HBLANK)
|
||||
newValue |= DISPSTAT_HBLANK_INTR;
|
||||
|
||||
if (oldValue != newValue)
|
||||
SetGpuReg(REG_OFFSET_DISPSTAT, newValue);
|
||||
}
|
||||
+2
-16
@@ -1,21 +1,7 @@
|
||||
gUnknown_3000000: @ 3000000
|
||||
.include "src/gpu_regs.o"
|
||||
|
||||
.space 0x4
|
||||
|
||||
gUnknown_3000004: @ 3000004
|
||||
.space 0x5C
|
||||
|
||||
gUnknown_3000060: @ 3000060
|
||||
.space 0x60
|
||||
|
||||
gUnknown_30000C0: @ 30000C0
|
||||
.space 0x1
|
||||
|
||||
gUnknown_30000C1: @ 30000C1
|
||||
.space 0x1
|
||||
|
||||
gUnknown_30000C2: @ 30000C2
|
||||
.space 0x6
|
||||
|
||||
gUnknown_30000C8: @ 30000C8
|
||||
.space 0xC
|
||||
|
||||
|
||||
Reference in New Issue
Block a user